Low-jitter clock design for high-speed ADC

introduction

　　ADC is the bridge connecting the analog signal processing part and the digital signal processing part in modern digital demodulators and software radio receivers. Its performance determines the overall performance of the receiver to a large extent. There are many sources of noise introduced during the A/D conversion process, mainly including thermal noise, ripple of the ADC power supply, ripple of the reference level, phase noise caused by sampling clock jitter, and noise caused by quantization errors. In addition to the inevitable noise introduced by quantization errors, many measures can be taken to reduce the noise power before reaching the ADC, such as using an amplifier with better noise performance, reasonable circuit layout, reasonable design of the sampling clock generation circuit, and reasonable design of the ADC. Power supply and use of decoupling capacitors, etc. This article mainly discusses the impact of sampling clock jitter on ADC signal-to-noise ratio performance and the design of low-jitter sampling clock circuits.

(a) Ideal signal-to-noise ratio of 12-bit ADC

(b) Measured signal-to-noise ratio of AD9245

Figure 1 Schematic diagram of the signal-to-noise ratio of the 12-bit ADC under different clock jitter conditions

Clock jitter on ADC

Effect of signal-to-noise ratio

　　 The jitter of the sampling clock is a short-term, non-cumulative variable that represents the time deviation between the actual timing position of a digital signal and its ideal position. The jitter generated by the clock source will cause the internal circuit of the ADC to trigger the sampling time incorrectly, resulting in missampling of the amplitude of the analog input signal, thereby deteriorating the signal-to-noise ratio of the ADC.
When the clock jitter is given, the maximum signal-to-noise ratio of the ADC can be calculated using the following formula:

　　According to formula (2), Figure 1 shows the ideal signal-to-noise ratio and the measured signal-to-noise ratio of the ADC under different clock jitter conditions when the number of quantization bits is 12-bit.

　　It can be seen from Figure 1 that the jitter of the clock has a very obvious impact on the deterioration of the signal-to-noise ratio performance of the ADC. The higher the frequency of the signal entering the ADC under the same jitter condition, the greater the deterioration of its performance. For the same input signal frequency, Under this circumstance, the greater the jitter of the sampling clock, the greater the deterioration of the ADC signal-to-noise ratio performance. Comparing the two schematic diagrams in Figure 1, we can see that the measured impact of sampling clock jitter on the ADC signal-to-noise ratio performance is very consistent with the results obtained from the theoretical analysis, which also proves the correctness of the theoretical analysis. Therefore, in actual applications, the A/D conversion chip cannot be selected entirely based on the ideal signal-to-noise ratio formula. Instead, one should refer to the measured performance curve given by the chip manufacturer and the jitter performance of the designed sampling clock to reasonably select the one that suits the design needs. A/D conversion chip, and leave a certain design margin.

Figure 2 A practical low-jitter clock generation circuit

Two practical low-jitter sampling clock generation circuit

clock jitter generation mechanisms

　　It is difficult to directly measure clock jitter, and indirect measurement methods are generally used. For this reason, this section first gives the generation mechanism of clock jitter. Clock jitter is caused by various noise sources inside the clock generation circuit (usually a phase-locked loop based on a low-phase noise voltage-controlled oscillator), such as thermal noise (mainly the thermal noise floor of the voltage-controlled oscillator output signal) , phase noise and spurious noise, etc. Theoretical analysis shows that when the required frequency is higher, the deterioration of clock jitter by phase noise and spurious noise is not obvious.

　　Generally speaking, the thermal noise floor of the VCO output stage amplifier can be regarded as Gaussian white noise with a limited bandwidth, and its effective bandwidth is approximately twice the operating frequency. When the VCO is correctly tuned to the desired output frequency, the effect of the noise floor on jitter can be calculated using the following formula:

　　In the formula, f0 is the center frequency of the oscillator, f represents the offset relative to the center frequency, and L(f) is the phase noise at the frequency offset f (unit is dBc/Hz). In order to further improve the performance of the system, people often use a power matching network with a frequency response similar to a band-pass filter at the output end of the VCO, which has a certain attenuation effect on noise outside the bandwidth. In this way, the worst-case noise can be estimated using the integral from 0 Hz to f0. The noise outside this range is greatly attenuated and can be ignored, because the noise floor from 0 to f0 is smooth, L( f) can be regarded as a constant, so formula (3) is simplified to:

　　Therefore, the edge clock jitter caused by the noise floor is:

　　Theoretically, it can be considered that the phase noise characteristics of the output signal from the phase-locked loop are basically the same as those of the VCO. However, the actual phase-locked circuit will introduce a certain amount of noise, and the VCO output amplifier will also worsen the phase noise characteristics of the generated clock signal. . Therefore, when designing a phase-locked loop circuit, in addition to choosing a VCO with lower phase noise, you should also choose an amplifier or clock buffer with a lower noise figure, and try to separate the clock generation circuit from other circuits. .

Variable sampling clock based on low phase noise VCO

　　Figure 2 shows a practical low-jitter variable sampling clock generation circuit based on a low-phase noise VCO.

　　In Figure 2, MC145170 is used as the frequency synthesizer for the clock generation loop, and Mini-Circuits company's low phase noise voltage controlled oscillator POS-200 is selected as the frequency synthesizer.

For the VCO of the clock generation loop, since the output signal of the POS-200 has to be branched multiple times, after the output signal is branched for the first time, one channel is fed back to the MC145170 as the input tuning signal, and the other channel is fed through the low-noise The amplifier amplifies the output, and then splits it again. One channel is used as the sampling clock of the ADC, and the other channel is sent to the DSP as the synchronization clock of the digital signal sampled by the ADC. From the above analysis, it can be seen that as long as it is properly designed, the phase noise characteristics of the output signal of the above clock generation circuit will mainly depend on POS-200. The single-sided phase noise of POS-200 at 1MHz deviated from the center frequency is -150dBc/Hz. This value can be used when estimating the thermal noise floor of the phase-locked loop circuit output signal. When the phase-locked loop output signal frequency is 81.92MHz, the jitter of the output clock signal can be calculated from formula (5) as:

　　If the ADC used is AD9245, it can be seen from Figure 1: When the ADC front-end input signal frequency is lower than 50MHz, the signal-to-noise ratio of AD9245 will be better than 65dB. When the input signal frequency is lower than 100MHz, the signal-to-noise ratio of AD9245 will be better than at 60dB.

Non-variable sampling clock based on extremely low phase noise temperature compensated crystal oscillator

　　After determining the sampling frequency, if the clock generated by the clock generation circuit is not required to be variable, a clock generation method based on a temperature-compensated crystal oscillator can be used. First, the maximum allowable clock jitter is determined based on the required ADC signal-to-noise ratio by formula (2), and then the maximum tolerated phase noise floor is deduced from formula (5). Finally, the phase noise characteristics at different frequency deviation points are given and intersected. It can be customized by the crystal oscillator manufacturing factory. This is the simplest time generation method, which basically does not require much debugging, but it is only suitable for fixed clock sampling.

　　When using the above two methods to generate a sampling clock, one thing worth noting is that the sampling clock circuit should be as independent as possible from the digital system with noise, and there should be no logic gate circuits in the path of the sampling clock. Generally speaking, , a logic gate will produce timing jitter of several picoseconds or even more than ten picoseconds. The sampling clock generation circuit should be separated from the digital and analog parts of the system during design.

Conclusion

　　This article first analyzes the impact of sampling clock jitter on ADC signal-to-noise ratio performance, then points out the reasons for the generation of time jitter, and finally gives two practical sampling clock generation solutions: a variable sampling clock based on low phase noise VCO and a variable sampling clock based on Method for generating a non-variable sampling clock from an extremely low phase noise temperature compensated crystal oscillator.

references

1 James Tsui．Translated by Yang Xiaoniu and others. Broadband digital receiver[M]. Beijing: Electronic Industry Press, 2002
2 AD9245 Datasheet．Analog Devices, Inc. 2003
3 Steve Lee, Ken Yang．Design a Low-Jitter Clock for High-Speed ​​Data Converters[J]．Maxim application note, 2001
4 Yang Xiaoniu, Lou Caiyi, Xu Jianliang. Principles and applications of software radio[M]. Beijing: Electronic Industry Press, 2001
5 Peng Fei. Research and implementation of bandpass sampling and digital down-conversion[D]. School of Communication Engineering, PLA University of Science and Technology, 2004