PCI9656 Introduction and Application Examples

PCI9656 is a 64-bit, 66MHz PCI interface circuit launched by PLX. It has flexible connection performance and high-performance I/O accelerator characteristics, and is used in PCI, Compact PCI and embedded host designs. This article mainly introduces the functions, features and applications of PCI9656 , gives specific application examples, and points out the problems that need to be paid attention to in the application.

introduction

The PCI bus protocol is relatively complex, so its interface circuit is difficult to implement. It not only has strict synchronization timing requirements, but also has many configuration registers to achieve plug-and-play and automatic configuration. For general designers, in order to shorten the development cycle, it is not necessary to design all the interface logic. As long as the general PCI interface circuit is used, the development and design can be carried out well, which greatly reduces the difficulty of the work.

At present, the interface chips that are widely used in the industry based on 32-bit PCI bus are AMCC's S59xx series and PLX's PLX series. However, all existing ordinary computer companies have adopted 32-bit architecture, and the system's memory addressing capacity has reached 4GB. Therefore, the 32-bit PCI bus can no longer meet the growing data processing needs. In view of the fact that the Itanium processor launched by Intel has directly jumped from 32 bits to 64 bits, it is particularly important to develop interface devices based on 64-bit PCI bus. The following introduces a PCI9656 interface circuit based on 64-bit PCI bus of PLX.

1 PCI9656 Overview

PCI9656 is an interface circuit that provides a hybrid high-performance PCI bus target mode for expansion adapter cards launched by PLX. This interface circuit can provide a small high-performance 64-bit PCI bus target interface for adapter cards. The internal structure block diagram of PCI9656 is shown in Figure 1. Its main features are as follows:

●Compliant with PCI V 2.2 protocol, supports 64-bit, 66MHz clock PCI bus, especially suitable for PCI bus peripheral product development.

●Adopts PLX Data Pipe Architecture technology, equipped with DMA engine, programmable direct master or direct slave data transfer mode and PCI information transfer function.

●With PCI priority decider, it can support 7 external master controllers.

●A PCI interrupt signal INTA can be generated by two local bus interrupt signals LINTi and LINTo.

●The local clock operates asynchronously with the PCI clock, allowing the local bus to operate independently of the PCI clock.

●Supports multiplexed and non-multiplexed 8-bit, 16-bit and 32-bit 66MHz clock local bus.

●Can directly generate all control, address and data signals to drive the PCI bus without the need for additional drive circuits.

● The I/O of the system can be managed through the message management system, and two methods are provided for selection: one is through the mailbox register and doorbell register, and the other is through the provided I2O interface.

●Registers are compatible with PCI9054 registers, making it easy to migrate software based on 32-bit PCI bus and 64-bit PCI bus.

2 Functions of PCI9656

PCI9656 can be used to provide data channels for non-PCI devices and PCI buses. The following describes the specific operation functions.

2.1 Initialization

When powered on, the RST signal of the PCI bus sets the internal registers of the PCI9656 to default values. At the same time, the PCI9656 outputs a local reset signal (LRESET) and checks whether the EEPROM exists. If the system is equipped with an EEPROM and the first 16 bytes of the EEPROM are not empty, the PCI9656 will set the internal registers according to the EEPROM contents, otherwise it will be set to default values.

2.2 Reset

When the RST signal of the PCI bus is valid, the entire PCI9656 will be reset, and at the same time, the LRESET local reset signal will be output. In addition, the master device on the PCI bus can also reset the PCI9656 by setting the software reset bit in the register, but the master device can only access the configuration register and cannot access the local bus. Therefore, the PCI9656 will remain in this reset state until the PCI master device clears the software reset bit.

2.3 Serial Memory Interface (EEPROM)

After reset, PCI9656 will start to read the serial EEPROM. START is 0, indicating that the EEPROM exists. At this time, if the first word (16 bits) of the EEPROM is neither "all 1" (EEPROM is empty) nor "all 0" (EEPROM does not exist), PCI9656 will use it for configuration. If START is 1, it means that the EEPROM does not exist or the EEPROM is empty, and PCI9656 uses the default value configuration.

The host on the PCI9656 bus can read and write the serial EEPROM. Register bits [31, 27-24] control the reading and writing of the EEPROM bits by the PCI9656. Setting the reload configuration register bit CNTRL[28] to 1 can reconfigure the PCI9656 with the serial EEPROM. The EEPROM clock can be obtained by dividing the PCI bus clock.