Design of digital frequency meter based on EDA technology

introduction

EDA technology is a new technology that uses large-scale programmable logic devices as design carriers, hardware language as the main way to describe system logic, computers, large-scale programmable logic device development software and experimental development systems as design tools. Through related development software, it automatically completes the design of electronic systems designed by software to hardware systems, and finally forms integrated electronic systems or dedicated integrated chips. Its design flexibility enables EDA technology to develop rapidly and be widely used.

This paper takes Max+PlusⅡ software as the design platform and adopts VHDL language to realize the overall design of digital frequency meter.

1 Working Principle

As we all know, frequency signals are easy to transmit, have strong anti-interference ability, and can obtain good measurement accuracy. Therefore, frequency detection is one of the most basic measurements in the field of electronic measurement. The basic principle of the frequency meter is to use a frequency source with high frequency stability as a reference clock to compare and measure the frequency of other signals. Usually, the number of pulses of the signal to be measured per second is calculated, that is, the gate time is 1 s. The gate time can be set as needed, and it can be greater or less than 1 s. The longer the gate time, the more accurate the frequency value obtained, but the longer the gate time, the longer the interval between each frequency measurement. The shorter the gate time, the faster the measured frequency value is refreshed, but the measured frequency accuracy is affected. Generally, 1 s is taken as the gate time.

The key components of a digital frequency meter include a frequency measurement control signal generator, a counter, a latch, a decoding drive circuit and a display circuit. Its principle block diagram is shown in Figure 1.

2 Design Analysis

2.1 Frequency measurement control signal generator

The control timing of the frequency measurement control signal generator to generate the measurement frequency is the key to designing a frequency meter. Here, the control signal CLK is taken as 1 Hz. After the frequency is divided by 2, it becomes a clock signal FZXH with a pulse width of 1 s, which is used as a counting gate signal. When FZXH is at a high level, counting starts; at the falling edge of FZXH, a latch signal SCXH is generated. After latching the data, a clear signal CLEAR is generated before the next rising edge of FZXH arrives to prepare for the next count. The CLEAR signal is valid on the rising edge.

2.2 Counter

The counter uses the signal to be measured FZXH as the clock, and is asynchronously cleared when the clear signal CLEAR arrives; it starts counting when FZXH is high. The maximum value of the counter designed in this paper is 99 999 999.

2.3 Latch

When the latch signal SCXH rises, the counter count value is latched, so that it can be decoded by an external seven-segment decoder and displayed on the digital tube. The advantage of setting a latch is that the displayed data is stable and will not flicker continuously due to periodic clearing signals. The number of bits of the latch should be exactly the same as that of the counter, both are 32 bits.

2.4 Decoding drive circuit

The digital tube in this article adopts dynamic display mode, and only one digital tube can be lit at any time. The digital tube bit selection signal circuit is a 74LS138 chip, and its 8 outputs are connected to the bit selection of 8 digital tubes respectively; 3 inputs are connected to the I/O pins of EPF10K10LC84-4 respectively.

2.5 Digital tube display

This article uses 8 common cathode digital tubes to display the value of the frequency to be measured, and the display range is from 0 to 99 999 999.

The following is the program for selecting the digital tube segment: