Low Noise Fractional-N Phase-Locked Loop Implementation

This circuit is a complete implementation of a low noise microwave fractional-N PLL with the ADF4156 as the core fractional-N PLL device. The PLL frequency range is extended to 18 GHz using the ADF5001 external prescaler. Using the ultra low noise OP184 op amp with proper biasing and filtering to drive the microwave VCO, a complete low noise PLL is achieved at 12 GHz with a measured integrated phase noise of 0.35 ps rms. This function is typically used to generate the local oscillator frequency (LO) for applications such as microwave point-to-point systems, test and measurement equipment, automotive radar, and military applications.

Figure 1. Low-Noise Microwave Fractional-N PLL (Simplified Schematic: Decoupling and All Connections Not Shown)

Circuit Description

Figure 1 shows the block diagram of the circuit. A 12 GHz VCO DXO11751220-5 from Synergy Microwave was selected for this circuit, although any VCO in the 4 GHz to 18 GHz range can be used as long as the loop filter is appropriately redesigned. Like most microwave VCOs, the Synergy VCO has a wide input tuning range of 0.5 V to 15 V, which requires an active PLL loop filter between the low voltage ADF4156 charge pump (maximum output of 5.5 V) and the VCO input. The OP184 was selected as the op amp for this active loop filter because of its good noise performance and rail-to-rail input/output. The op amp output noise will feed through to the RF output and be shaped by the active filter response, so the noise is low. Rail-to-rail input operation is also an important consideration for the PLL active filter because a single op amp supply can be used. This is because the charge pump output (CPOUT) will start at 0 V on power-up, which can be problematic for op amps that do not have a rail-to-rail input voltage range. This also allows the noninverting input of the op amp to be biased above ground with built-in margin for any bias voltage variations due to resistor mismatch or temperature changes. It is recommended that the bias level be set to approximately half of the charge pump supply (VP) to meet the input voltage range requirements with ample margin and to achieve the best charge pump spurious performance. This circuit note was measured with VP = 5 V and the op amp common-mode bias voltage = 2.2 V. To minimize reference noise feedthrough, a large 1 μF decoupling capacitor is placed close to the noninverting op amp input pin, as shown in Figure 1. This capacitor and the 47 kΩ resistor form an RC filter with a cutoff frequency below 10 Hz.

Loop Filter Design

The circuit selected an inverting topology with prefiltering. Prefiltering is recommended to avoid overdriving the amplifier with very short current pulses from the charge pump, which could limit the slew rate of the input voltage. When using an inverting topology, it is important to ensure that the PLL IC allows the PFD polarity to be reversed to cancel out the inversion of the op amp and drive the VCO with the correct polarity. The ADF4156 PLL has this PD polarity option.

Common changes

Several active loop filter topologies are available in ADIsimPLL using either inverting or noninverting op amp configurations. Phase noise trade-offs can be analyzed in ADIsimPLL. The inverting topology allows output voltages down to the minimum output voltage of the op amp, which can be as low as 125 mV for the OP184. In contrast, the output voltage of the noninverting topology is limited to the product of the minimum charge pump voltage (0.5 V) and the noninverting gain.

Setup and Measurement

Table 1 shows the circuit setup, and Figure 2 shows the measured results compared to the simulated performance predicted by ADIsimPLL, showing very good agreement. The measured integrated phase noise is 0.35 ps rms. The measurement setup is shown in Figure 3.

Table 1. Test measurement setup

The performance of this or any high speed circuit is highly dependent on proper PCB layout. This includes, but is not limited to, power supply bypassing, controlled impedance lines (where required), component placement, signal routing, and power and ground planes.

Figure 2. Measured vs. simulated phase noise performance of a 12 GHz PLL.

Figure 3. Measurement circuit