Typical application circuit design of IDT70V9289

IDT70V9289 is a high-speed synchronous dual-port static RAM ( SRAM ) newly launched by IDT , which can realize lossless transmission of dual-channel high-speed data streams in different transmission modes. This paper introduces the structure and principle of the circuit in detail, gives the typical application circuit of IDT70V9289 and the problems that should be paid attention to in design.

1 Introduction

With the development of science and technology and the continuous emergence of high-speed devices, data transmission rates are getting higher and higher. Due to the different transmission methods, it is very important whether various high-speed devices can achieve reliable data exchange when connected. The emergence of high-speed dual-port SRAM provides an effective way to solve this problem. IDT70V9289 is a new high-speed synchronous dual-port static memory launched by IDT. Its capacity is 64k×16bit, with the characteristics of simple design and flexible application.

2 Structure and Function of IDT70V9289

2.1 Internal structure

Figure 1 shows the block diagram of the IDT70V9289, which is mainly composed of an I/O controller, a memory array, a counter/address register, and some logic circuits.

2.2 Features

True dual-port memory, fully synchronous operation

3.5ns clock setup time, 0ns hold time (all control, data and address inputs)

With data input, address and control registers

Storage capacity up to 1024kbit (64k×16bit);

High-speed data access, its TCD (delay between clock rising edge and data input/output) is

Commercial grade: 6/7.5/9/12ns (max)

Industrial grade: 9ns (max)

·Using IDT's high-performance CMOS technology, low power consumption

Working: 500mW (typical)

Standby: 1.5mw (typical)

Count enable and reset functions

· Select flow-through or pipeline output mode for any port via FT/PIPE pin

Independent high and low byte control in multiplexed buses

LVTTL interface level, 3.3V (±0.3V) single power supply

2.3 Pin Function (Take the left port pin as an example)

VDD: Power input terminal. The bypass capacitor that acts as a filter should be as close to the power pin as possible and directly connected to the ground.

VSS: ground pin;

CE0L, CE1L: Enable pin, when CE0L is low and CE1L is high, the circuit works. This pin allows the on-chip circuit of each port to enter a low-power standby mode;

R/WL: Read/write enable, read when this terminal is high, write when it is low;

OEL: asynchronous output enable;

A0L-A15L: address synchronization input terminal;

I/O0L-I/O15L: data input/output terminal;

CLK: Memory working clock, so the input signal is valid on the rising edge of this clock;

UBL: high byte selection, low level is valid;

LBL: low byte selection, low level is valid;

CNTENL: counter enable. When the clock rises, if the pin is low, the address counter works and has a higher priority than other pins.

CNTRSTL: counter reset, low level is valid, priority is higher than other pins;