Improved TTL gate circuit—anti-saturation TTL circuit

The anti-saturation TTL circuit is a type of TTL circuit with a relatively high transmission speed. This circuit uses the Schottky barrier diode SBD clamping method to achieve the anti-saturation effect. It is generally called SBDTTL circuit (abbreviated as STTL circuit). Its transmission speed is much higher than that of the basic TTL circuit.

The working characteristics of the Schottky barrier diode are as follows:
(1) Like the PN junction, it also has unidirectional conductivity. The direction of the conduction current of this aluminum-silicon barrier diode is from aluminum to silicon.
(2) The conduction threshold voltage of the AL-SiSBD is low, about 0.4~0.5V, which is about 0.2V lower than that of the ordinary silicon PN junction.
(3) The conductive mechanism of the barrier diode is the majority carrier, so the charge storage effect is very small.
According to the previous study, we already know that when the BJT works in saturation, the emitter junction and the collector junction are both in forward bias. The larger the forward bias voltage of the collector junction, the deeper the saturation.
In order to limit the saturation depth of the BJT, a Schottky diode with a low conduction threshold voltage is connected in parallel to the base and collector of the BJT, as shown in the figure below.

When there is no SBD, as the base voltage increases, the current flows along the blue line. Due to the function of SBD, when the base voltage is greater than 0.4V, SBD is first electrically conductive, and the current flows along the red line (as shown in the figure below), so that the base current of T will not be too large (and the forward bias voltage of the collector junction of T will be clamped at about 0.4V). Therefore, SBD plays a role in resisting oversaturation, so this circuit is also called anti-saturation circuit , which greatly shortens the switching time of the circuit.

The following figure shows a typical circuit of Schottky TTL (STTL) NAND gate. Compared with the basic TTL NAND gate circuit, several improvements have been made. In the basic TTL circuit, T1 _, T2 _and T3 _work in the deep saturation region, and the charge storage effect in the tube has a great influence on the switching speed of the circuit. Now, except for T4 _, the rest of the BJTs use SBD clamping to achieve a significant anti-saturation effect. Secondly, all the resistance values ​​in the basic circuit are almost halved here. These two improvements lead to a significant reduction in the switching time of the gate circuit. The reduction in resistance value will inevitably lead to an increase in the power consumption of the gate circuit.

The STTL gate circuit has the following three improvements over the performance of the basic TTL circuit:
(1) The diode D is replaced by a compound tube composed of T4 _and T5 _. When the output transitions from a low level to a high level, the current gain of the compound tube circuit is large and the output resistance is small
, thereby reducing the circuit's charging time for the load capacitance. (2) The SBD- _DA and _DB
added to the input of the circuit are used to reduce the stray signals caused by the connection between the gate circuits. (3) _Re2 (1kΩ) in the basic circuit is replaced by a combination circuit of _{T6 , Rc6} , and _Rb6 . This combination circuit is an active nonlinear resistor. When the voltage across it (emitter e2 to ground) is low, it presents a large resistance, and when the voltage across it reaches about 0.7V, it presents a small resistance. In this way, when all the inputs of the NAND gate turn from low level to high level, the active resistor starts to be non-conductive and T3 _quickly reaches saturation; on the contrary, when all the inputs of the circuit (or one of them) turn from high level to low level, T2 _and T3 _will be cut off. Since VBE = 0.7V when T3 _{is saturated} , the resistance of the active resistor is very small at the moment of the conversion, and the charge stored in the _base region of T3 quickly dissipates through this low resistance loop. For this reason, the active nonlinear circuit is called an active pull-down circuit, which corresponds to the active pull-up circuit. This means that VBE3 _is quickly pulled from 0.7V to 0V, so that the output voltage rises quickly, that is, the switching speed is increased.

Based on the above characteristics, the STTL NAND gate has a relatively ideal transmission characteristic. Compared with the transmission characteristic of the basic TTL inverter, point C no longer exists, and it drops directly from point B to point D, that is, the transmission characteristic changes very steeply, as shown in the figure below.

In addition to the typical Schottky type (STTL), there are also low-power Schottky type (LSTTL), advanced Schottky type (ASTTL), advanced low-power type (ALSTTL), etc. Their technical parameters have their own characteristics and are gradually formed in the development of TTL technology.

Performance comparison of various series of TTL gate circuits