MCS-51 Single Chip Microcomputer and FPGA

1. Interface between MCU and FPGA

There are generally two ways to interface a single-chip microcomputer with an FPGA, namely the bus method and the independent method. The MCS-51 single-chip microcomputer has a strong external bus expansion capability. It is easy to realize the bus interface between the single-chip microcomputer and the FPGA using the three-bus structure outside the chip. In addition, the single-chip microcomputer has many advantages in communicating data and control information with the FPGA in bus mode: fast speed; saving the I/O port lines of the PLD chip; compared with the non-bus method, the single-chip microcomputer is easy to program and the control is reliable; through logical switching in the FPGA, the single-chip microcomputer is easy to interface with SRAM or ROM.

In the logic design of the communication between the microcontroller and the FPGA in bus mode, it is important to understand the bus read/write timing of the microcontroller in detail, design the logic structure according to the timing diagram, and the communication timing must follow the fixed bus read/write timing in the microcontroller. The logic design of FPGA is also relatively complex. In terms of program design, it must be combined with the microcontroller program of the interface, and the I/O space that the microcontroller can access must be strictly arranged. When the microcontroller communicates and controls data with the FPGA in bus mode, its communication working timing is pure hardware behavior, and the speed is much faster than the previous method. In addition, if enough decoding outputs are set inside the FPGA, the microcontroller can communicate and control information exchange between the FPGA and the microcontroller through only 19 I/O lines, which can save the I/O lines of the FPGA chip. Its schematic diagram is shown in Figure 1.

2 Bus Interface Logic Design

2.1 Interface design concept

In the logic design of bus communication between MCU and CPLD/FPC, it is important to understand the bus read and write timing of MCU in detail and design the logic structure according to the timing diagram. The timing diagram of MCS-51 series MCU is shown in Figure 2.

ALE is the address latch enable signal, and its falling edge can be used to latch the lower 8-bit address into the address latch (LATCH_ADDRES) in the FPGA; when ALE latches the lower 8-bit address through P0, the upper 8-bit address has been stably established at the P2 port, and the microcontroller uses the low level of the read instruction enable signal PSEN to read the instruction from the external ROM from the P0 port. As can be seen from the timing diagram, the timing of the instruction reading is before the rising edge of PSEN. Next, the upper 8-bit and lower 8-bit data addresses are output from the P2 port and the P0 port respectively, and the lower 8-bit address of the P0 port is latched into the address latch by the falling edge of ALE. If data needs to be read from the FPGA, the microcontroller uses the instruction "MOVXA, @DPTR" to make the RD signal low, and the P0 port reads the data in the latch into the accumulator A; but if the data of the accumulator A is to be written into the FPGA, the instruction "MOVx DPTR, A" and the write enable signal WR are required. At this time, the high 8-bit and low 8-bit data in DPTR are output to P2 and P0 ports as high and low 8-bit addresses respectively, and then the low level of WR is combined with decoding to write the data of accumulator A into the relevant latch in the figure. [page]

By analyzing the read/write timing of the MCS-51 microcontroller bus, the interface circuit shown in Figure 3 was designed. In the FPGA, two modules are designed: one is the bus interface module, which is responsible for the bus interface logic between the microcontroller and the FPGA; the other is the register unit and external interface module, which is operated by the bus interface module.

In bus applications, the P0 port of the MCS-51 microcontroller is used as the address/data bus for time-sharing multiplexing, so a three-state buffer should be designed in the bus interface module to realize the three-state interface of the P0 port; and because the address of the MCS-51 microcontroller is 16 bits when accessing the external space, the address latch enable signal ALE is used to encode the high 8-bit and low 8-bit addresses in the FPGA and combine them into a 16-bit address, and then the read/write operations on the FPGA are realized according to the read/write signals of the MCS-51 microcontroller.

In the interface design, VHDL language is used to implement its interface logic. Writing in VHDL language is often more convenient and rigorous. Pay attention to the logical thinking of the whole process and try to avoid language redundancy, which will cause a long delay. -Part of the program of the communication read-write circuit between MCS-51 microcontroller and FPGA

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FPGA is a new type of programmable logic device that can replace all existing microcomputer interface chips and realize multiple functions such as memory and address decoding in microcomputer systems. It has higher density, faster working speed and greater programming flexibility, and is widely used in various electronic products. In terms of function, the single-chip microcomputer has the characteristics of high cost performance, flexible functions, easy human-computer dialogue, and powerful data processing capabilities; while FPGA has the characteristics of high speed, high reliability, convenient development, and standardization. Therefore, the circuit structure combining the two types of devices will be widely used in many high-performance instruments and electronic products. Based on this demand, this paper designs the bus interface logic circuit between the MCS-51 single-chip microcomputer and FPGA, realizing the reliable communication of data and control information between the single-chip microcomputer and FPGA, making the advantages of FPGA and single-chip microcomputer complement each other, forming a flexible control system that can be programmed on-site in both software and hardware.