Optimization Method of Soft Clock Design in MCS-51 Single Chip Microcomputer

0 Introduction

With the popularization of microcomputer applications, microcomputer measurement and control systems with MCS-51 single-chip microcomputer as the core can be seen everywhere. To meet user requirements, these systems usually have the function of digital display clock. Since MCS-51 contains two timing counters, the method of using one of the timing counters for soft clock design can greatly save hardware costs. This paper proposes how to improve the timing accuracy of soft clock, and how to improve the design quality of measurement and control systems with MCS-51 single-chip microcomputer as the core in the presence of soft clock.

1 Overview of the internal timing counters of the MCS-51 microcontroller

The MCS-51 microcontroller contains two timing counters T0 and T1, which are both 16-bit adder counters that can be used for both timing and counting. When used for timing, the counting pulse is provided internally, so the counting rate is fixed at 1/12 of the CPU oscillation frequency; when used for counting, the counting pulse comes from the outside, and the external counting pulse is input through the pin T0 (pin 14) or T1 (pin 15) of the MCS-51. When a jump from 1 to 0 occurs, the count is increased by 1. Each timing counter has 4 working modes to choose from: Mode O constitutes a 13-bit timing counter, and the upper 3 bits are not used; Mode 1 constitutes a 16-bit timing counter; Mode 2 constitutes an 8-bit timing counter, the low byte is used for counting, and the high byte stores the initial value; Mode 3 is only suitable for T0, constituting two independent 8-bit timing counters. In mode 0, mode 1 and mode 3, the initial value cannot be automatically loaded. When the timing time has expired or the count times have been full, if you want to perform the next timing count, you must use software to load the initial value, otherwise, the system will automatically time or count according to the upper limit, that is, time or count with the initial value of 0; in mode 2, the initial value can be automatically loaded. You only need to write the initial value to the high byte once. When the low byte timing time is up (or the count is full), the initial value of the high byte will be automatically loaded into the low byte, and the value of the high byte remains unchanged. When the system needs to use the serial interface of the MCS-51 microcontroller for serial communication, the timing counter T1 is fixed as the baud rate generator. Therefore, in the soft clock design, T0 is always selected as the timer.

2 Soft clock programming method 1 -

0.1 s counting method The basic principle of the 0.1 s counting method is as follows: by setting the timer counter O to request an interrupt every 0.1 s, the interrupt handler will increase the base 0.1 s unit of the soft clock by 1, and every 10 times the unit increases, the second unit of the soft clock will increase by 1, and so on, according to the time carry, the minute, hour, day, month and year units will increase by 1. Assuming the oscillation frequency of the crystal oscillator connected to the CPU is 6 MHz, then one machine cycle is 2μs. When T0 works as a timer, the timer overflows, that is, the interrupt cycle: T=2×TC×10-6 s, where TC is the time constant. Let the interrupt cycle T=0.1 s, we can get: TC=0.1/(2×10-6)=50 000=0C350H. This time constant determines that T0 must be a 16-bit timer, so it is set to work mode 1. Since it is an addition counter, the initial value IC should be the complement of the time constant TC, so IC=216-TC=10000H-0C350H=3CBOH. After correction, IC=3CB4H is taken. The specific design of the relevant program segment is as follows.

Initialization program:



From the above program, it can be seen that when used as a 16-bit timer, T0 cannot automatically load the initial value. Each time after entering the interrupt service program, the initial value must be loaded by the program first. The next timing actually starts after the initial value low byte is loaded. Therefore, under the ideal condition that the T0 interrupt is set to high priority and the CPU responds to the T0 interrupt request without waiting delay, the actual time t included in one interrupt cycle = the time required from the initial value to the full count + the entry boot time + the time to load the initial value low byte.

Since the entry boot and the loading of the initial value low byte occupy 4 machine cycles, in order to make the interrupt cycle equal to the 0.1s reference time, the initial value calculated according to the theory is corrected by adding 4. Nevertheless, it is very difficult to achieve accurate timing when the clock program designed according to method 1 is organically connected with other programs of the measurement and control system, because in practical industrial measurement and control systems, there are often more than one interrupt source, but multiple interrupt sources, and there is a problem of interrupt priority management. In order to enable the above soft clock to accurately time, the T0 interrupt must be set to a high priority, so that the CPU's timing interrupt to T0 is not affected, ensuring that the timing interrupt service program is executed every 0.1 s. If the T0 timing interrupt is set to a low priority, the CPU's response to the T0 timing interrupt will be affected. When the CPU is executing the interrupt service program of a high-priority interrupt source, an interrupt request will be generated when the T0 count is full. The CPU must wait until the currently executing interrupt service program is completed before responding to the T0 interrupt, which will inevitably extend the interrupt interval, so that the initial value cannot be loaded as expected, and the timing accuracy is destroyed. It can be seen that the clock program designed by method 1 limits the flexibility of the system in setting interrupt priority and reduces the design efficiency. For example, some measurement and control systems that use digital tubes as displays usually use the method of scanning the digital tubes for display output in order to save hardware costs. In order to make the display stable and without jitter, the digital tube display interrupt must be set to a high priority to ensure that the execution cycle of the scanning program is fixed, which conflicts with the priority requirements of the clock timing interrupt. In order to overcome the defects of method 1, in actual engineering, better results can be obtained by designing the clock program using method 2 as described below.

3 Soft clock program design method 2-interrupt cycle accumulation method The

program structure of method 2 and method 1 is exactly the same, except for the difference in the processing of time below seconds. Change the "O.1 s unit increase by 1" program segment in the interrupt service program of method 1 to:



It is easy to see by comparison that although the two "O.1 s unit increase by 1" program segments use different instructions, the effects are exactly the same and can be replaced by each other. The modified program changes the counting of the 0.1 s interrupt cycle to the counting of the O.1 s interrupt cycle. 1 s interrupt cycle accumulation, from which, any interrupt cycle less than a second can be accumulated, when the highest bit has a carry, the second is increased by 1, which can also achieve the purpose of clock timing. When the internal timer of the MCS-51 microcontroller selects working mode 1, it is a 16-bit counter. Under the above assumptions, when the initial value is 0, the timing interrupt cycle T of T0 is T=0.131 072 s, and 131072 is defined as the interrupt cycle constant, which is accumulated in the interrupt service program. The following is the clock program designed using method 2. Define the

interrupt cycle constant:

CONST: DB 00H, 13H, 10H, 72H

Initialization program:



Method 2 uses the method of accumulating interrupt cycles to make the timer count at full scale, with an initial value of 0. After counting is full, it automatically starts counting from 0 again. There is no need to load the initial value with the program, which fundamentally gets rid of the trouble of loading the initial value, and of course avoids the tedious process of correcting the initial value. Since there is no need to load the initial value, the CPU can respond to the timer's interrupt request at any time during the interrupt cycle. It only needs to ensure that the interrupt service program is executed before the next interrupt request arrives, which greatly reduces the interrupt priority requirement of the timer. Therefore, method 2 sets the timer interrupt to a low priority, while method 1 sets it to a high priority. Obviously, using method 2 is not only convenient for program design, but also improves the efficiency of program design.

In method 2, when the timer counts at full scale, the interrupt cycle is no longer the standard 0.1 s. Therefore, the carry of the interrupt cycle to the second unit during the accumulation process mostly occurs at non-integer seconds, and the carry interval is also different. Specifically, assuming that the time unit below the second starts to accumulate from 0, the first carry to the second unit is at 1.048 576 s, the second at 2.097 152 s, and the third at 3.014 656 s, ..., the interval between the first and second is 1.048 576 s, the interval between the second and third is 0.917 504 s, ..., the carry interval is sometimes greater than 1 s, and sometimes less than 1 s. However, for long-term time processes such as minutes, hours, days, and months, the accumulated error can be considered equal to 0. In this sense, method 2 greatly improves the timing accuracy.

4 Conclusion

The method of using the internal timing counter of MCS-51 as the soft clock design is proposed, which not only saves hardware overhead, but also improves the timing accuracy of the soft clock, and has a wide range of application value. In actual tests, when the oscillation frequency of the crystal oscillator is not the standard 6 MHz, the interrupt cycle constant can be made accurate to the required precision by adjusting the interrupt cycle constant and, if necessary, increasing the number of bytes in the sub-second time unit buffer.