Interrupt handling study notes

Interrupt handling

If you want to use interrupts:

1 Initialization

ASet the source

View Schematic

XEINT0/kpROW0/GPN0

View chip manual

Enable

B. Set up the interrupt controller

This chapter describes the functions and usage ofVectored Interrupt Controller in S3C6410X RISC

microprocessor.

12.1 OVERVIEW

The interrupt controller in the S3C6410X is composed of2 VIC’s (Vectored Interrupt Controller, ARM PrimeCell

PL192) and 2 TZIC’s (TrustZone Interrupt Controller, SP890).

Two TZIC’s and VIC’s are daisy-chained to support up to 64 interrupt sources.

12.2 FEATURES

The Vectored Interrupt Controller features in S3C6410 incudes the following:

• Support for 32 vectored IRQ interrupts per VIC

• Fixed hardware interrupt priority levels

• Programmable interrupt priority levels

• Hardware interrupt priority level masking

• Programmable interrupt priority level masking

• IRQ and FIQ generation

• Software interrupt generation

• Raw interrupt status

• Interrupt request status

• Privileged mode support for restricted access

C Turn on the I status bit in cpsr (clear)

If an outage occurs:

1 cpu enters irp mode

2 cpsr saved to spsr_irq

3 Use r13_irq, r14_irq

4 Store the next instruction address in r14

5 Jump to 0x18 to execute

Save interrupt

Handling interrupts

Recovering from interruption

Interrupt Vector Register