Memory management mechanism of s3c2440

1. Differences between Nand Flash, Nor Flash and SDRAM addresses

Nand Flash: ROM, large capacity, suitable for data storage. ARM cannot be started directly from Nand. It is necessary to copy the program from the first 4k space of Nand to SDRAM, and then start from SDRAM.

Nor Flash: ROM, small capacity, suitable for program storage, ARM can be started directly from Nor Flash.

SDRAM: RAM, large capacity, large software such as operating system runs in SDRAM.

2. S3c2440 addressing space:

S3C2440 has 27 address lines ADDR[26:0] and 8 chip select signals ngcs0-ngcs7, corresponding to bank0-bank7. When accessing the address space of bankx, the ngcsx pin is low and the peripheral is selected.

2^27=2^7 * 2^10 * 2^10 = 128Mbyte

8*128Mbyte = 1Gbyte

So the total addressing space of S3C2440 is 1Gbyte. (That is, the highest address is 0x40000000)

The addressing space is as follows:

3. SDRAM addressing principle:

SDRAM has a storage array inside. You can think of it as a table. Just like the retrieval principle of a table, you can find the required storage unit accurately by specifying the row first and then the column. This table is called a logical bank. Currently, SDRAM basically has 4 banks. The addressing process is to specify the bank address first, then the row address, and finally the column address. This is the addressing principle of SDRAM.

4. Connection method of memory chip (HY57V561620F):

The capacity of HY57V561620F is 16M addressing * 16-bit width = 256Mbit.

Two memory chips are used in TQ2440, with a total capacity of 2*32M=64Mbyte.

A0-A12 are address lines: row address and column address are multiplexed, row address uses A0-A12 (13 lines), column address uses A0-A8 (9 lines).

BA0-BA1 are bank select pins. (Bank select is sent at the same time as the row address, and has other uses when the column address is sent).

This SDRAM has

13 row address lines RA0-RA12

9 column address lines CA0-CA8

2 BANK selection lines BA0-BA1

The address pins of SDRAM are multiplexed. When reading and writing SDRAM storage cells, the operation process is to input the read and write addresses into the chip twice, each time by the same set of address lines. The addresses sent to the chip twice are called row addresses and column addresses. They are latched into the row address latch and column address latch inside the chip. /RAS is the row address latch signal, which latches the row address in the row address latch inside the chip; /CAS is the column address latch signal, which latches the column address in the column address latch inside the chip.

SDRAM A0 is connected to S3C2440 ADDR2, many beginners have questions about this. Why doesn't A0 connect to ADDR0?

To understand this connection method, you must first understand that in the CPU's addressing space, byte (8 bits) is the only unit for representing storage capacity.

Using two HY57V561620F chips to expand into 32-bit SDRAM, we can assume that each storage unit is 4 bytes. Therefore, when its address line A1:A0=01, the corresponding address line on the processor should be ADDR3:ADDR2=01 (32-bit SDRAM has one address for every 4 bytes, corresponding to the CPU) (because the addressing space of the CPU is in bytes). Therefore, the A0 pin of the SDRAM is connected to the ADDR2 address line of the S3C2440.

(It can be seen that ARM's addressing address = CPU's address * 4, because for the CPU it is equivalent to a 4-byte interval between each read).

Similarly, if you use one HY57V561620F, the data line is 16 bits, because one storage unit is 2 bytes, then the A0 of SDRAM should be connected to the ADDR1 of S3C2440.

That is to say, which address line of S3C2440 is connected to SDRAM A0 is determined by the data bit width of the entire SDRAM.

In the wiring diagram above, BA0 and BA1 are connected to ADDR24 and ADDR25. Why are these two address lines used?

BA0~BA1 represent the highest address bit of SDRAM. Because the addressing space of CPU is in byte, the SDRAM capacity of this system is 64MByte, so A25~A0 (64M=2^26) address lines are needed for addressing, so BA1~BA0 address lines should be connected to ADDR25~ADDR24 pins of 2440.

13 row address lines + 9 column address lines = 22. In addition, one storage unit of HY57V561620F is 2 bytes, which is equivalent to 23 address lines. BA0 and BA1 are the highest address bits, so they should be connected to ADDR24 and ADDR25.

5. Addressing mode during startup

System startup depends on the values ​​of the OM0 and OM1 pins of the S3c2440 CPU:

Therefore, in TQ2440, OM1 is directly grounded (always 0), and OM0 is used as a dip switch to select whether to start from nand (grounded, 0) or from nor 32-bit (floating, 1).

6. Nor Flash pin diagram (EN29LV160AB-70TCP)

Address lines A0-A19, 20 in total;

Data lines D0-D15, a total of 16 (D15 is data and address multiplexing);

When BYTE# on pin 47 is configured in byte mode (0), D15 is used for the A-1 address line, so the addressing space is 20+1=21, or 2M bytes.

When the BYTE# pin 47 is configured as double word mode (1), D0-D15 are used for data lines, the addressing space is 20 lines, 1M, data lines D0-D15 are valid, and the data volume is 1M*2=2Mbyte. (TQ2440 uses this mode)

7. Important Information Address

Memory allocation

8. Glossary