First of all, the S3C2440 memory space does not include NAND FLASH, NAND FLASH is just a peripheral.
The addressing range of the S3C2440 memory controller is 0~0x3fff ffff, a total of 1G. This 1G space is divided into 8 banks, BANK0~BANK7.
During the product development stage, BANK0 is generally used to control NOR FLASH and BANK6 to control SDRAM. For the finished product, NOR FLASH will be removed and the firmware will be placed on NAND FLASH, while SDRAM remains unchanged.
For code storage, such as NOR FLASH, it is not necessary to access specific bytes; for SDRAM, because byte variables may be stored, byte access must be supported. Here we will talk about how the memory controller accesses the bytes of SDRAM under a 32-bit bus width.
For example, two 16-bit SDRAMs are used to form a 32-bit data bus. The address lines A0 and A1 of S3C2440 are no longer used. S3C2440 provides DQM0, DQM1, DQM2 and DQM3 to select a certain byte (guess: DQM0, DQM1, DQM2 and DQM3 are obtained from A0 and A1 through the internal decoder, which can save external components). Then expand the row and column addresses of SDRAM, and add the selection line of SDRAM BANK, and SDRAM can actually be regarded as a SRAM.
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