IMX6ULL Bare Metal-3-SPI Controller

1 IMX6ULL SPI controller

Chapter 20 of NXP's 6ull reference manual introduces the SPI controller, Enhanced Configurable SPI (ECSPI).

1.1 Features

①. Full-duplex synchronous serial interface. ②. Configurable master/slave mode. ③. Four hardware chip select signals, support multiple slaves. ④. There is a 32x64 FIFO for both sending and receiving. ⑤. The polarity phase (CPOL, CPHA) of the chip select signal SS/CS and the clock signal SCLK are configurable. ⑥. Support DMA ⑦. SCK can be as high as the input reference clock of 60Mhz

1.2 Block Diagram

On the far right are the pins, SCLK, MISO, MOSI, etc. Above are the peripheral buses, registers are read and written through the APB bus, INTREG, CONREG, etc. The TXDATA and TXDATA registers store the data to be sent and the received data. The clock source comes from the Reference Clock or Low Frequency Clock. The optional clock sources are as follows: Here, ecspi_clk_root is selected.

① Set the ECSPI_CLK_SEL bit of CSCDR2 to 0, and select PLL3_SW_CLK to divide by 8 as the ECSPI root clock source. PLL3_SW_CLK=480MHz, 8-division is 60MHz. ② The ECSPI_CLK_PODF bit of CSCDR2 is divided again, and the ECSPI_CLK_PODF bit is set to 0, indicating 2^0 division, that is, 1 division. ③ Finally, ECSPI_CLK_ROOT is 60MHz

1.3 Timing

The CPOL clock polarity and CPHA clock phase are combined into 4 modes:

CPOL: indicates the initial level of SPI CLK (level in idle state), 0 is low level, 1 is high level
CPHA: Indicates the phase, that is, whether the first or second clock edge samples the data, 0 is the first clock edge, 1 is the second clock edge

2 IMX6ULL SPI controller register description

Controller initialization process: CONREG[EN]: reset, 0 means reset CCM to start ECSPI clock CONREG[EN]: reset, 1 means reverse reset

RXDATA register: receive data register, the state of the RR bit determines whether the received data is ready

TXDATA register: transmit data register. The actual number of bits transmitted is determined by the BURST_LENGTH bit of the corresponding SPI control register.

CONREG register: control register

EN: Enable bit, 1 is enabled SMC: 1 means that when data is written to TXFIFO, the SPI burst is started immediately; this mode is used here CHANNEL_MODE: Hardware chip select mode selection, bit[7:4] represents channel 3 to channel 0 respectively, and channel 0 is set to Master mode here. Therefore, bit[7:4] is configured to 1 POST_DIVIDER: Post-division, 0 to 15 represents 2^n power division, for example, 0 is 1 division, 15 is 2^15 division PRE_DIVIDER: Pre-division, 0 to 15 represents 1 to 16 division The clock source of the previous spi clk is ECSPI_CLK_ROOT 60MHz, here we use 6MHz, so we can set POST_DIVIDER=0, PRE_DIVIDER=9, indicating 10 division. CHANNEL_SELECT: Channel selection, that is, hardware chip select SS selection, here select SS0, channel 0 BURST_LENGTH: Burst access length, here we use a burst of 8 bits, configured to 0x7

CONFIGREG register: configuration register

SCLK_PHA: Clock phase, SCLK_PHA[3:0] corresponds to channels 3~0 respectively. Setting it to 0 means collecting data on the first clock edge, and setting it to 1 means collecting data on the second clock edge. (To form 4 modes with POL) SCLK_POL: Clock polarity, indicating the level when the clock is initially idle, 0 is low level, 1 is high level. (To form 4 modes with PHA) SS_CTL: Wave form select for hardware chip select, this is not used, set to 0 SS_POL: Polarity selection for hardware chip select, this is not used, set to 0 DATA_CTL: Level state when the data line is idle, we set it to 0 to indicate a high level SCLK_CTL: Level state when the clock line is idle, we set it to 0 to indicate a low level (POL sets the level when the clock is initially idle to a low level) HT_LENGTH: Not used in HT Mode, no configuration required

STATREG register: status register

TE:TXFIFO empty, 1 means TXFIFO is empty, 0 means TXFIFO is not empty yet, so when sending data to TXDATA, you need to wait for TXFIFO to be empty first. RR: RXFIFO Ready, 1 means there is data, 0 means data is not ready yet. Reading RXDATA requires waiting for RXFIFO to be ready first.

PERIODREG Register: Sampling Period Register

SAMPLE_PERIOD: The waiting period for burst access, which indicates how many clock cycles to wait before the next burst access. We set it to 0x2000.

CSRC: Waiting cycle unit, 0 means SPI clk as the unit, 1 means low-frequency reference clk 32.768KHz as the unit. CSD_CTL: Hardware chip select delay, indicating how many clock cycles after chip select can data be transmitted. (Not used here, we use software chip select)

3 IMX6ULL SPI controller code writing

void spi_init(ECSPI_Type *base)

{

/* Configure CONREG register

* bit0: 1 Enable ECSPI

* bit3: 1 Start SPI burst immediately after writing data to TXFIFO.

* bit[7:4]: 0001 SPI channel 0 master mode, select according to actual situation,

* The ICM-20608 on the development board is connected to SS0, so set channel 0 to master mode

* bit[19:18]: 00 selects channel 0 (not necessary, because the chip select signal is controlled by ourselves)

* bit[31:20]: 0x7 The burst length is 8 bits.

*/

base->CONREG = 0; /* Clear the control register first */

base->CONREG |= (1 << 0) | (1 << 3) | (1 << 4) | (7 << 20); /* Configure CONREG register */

/*

* ECSPI channel 0 settings, that is, setting the CONFIGREG register

* bit0: 0 Channel 0 PHA is 0

* bit4: 0 Channel 0 SCLK high level is valid

* bit8: 0 Channel 0 chip select signal. This bit is invalid when SMC is 1.

* bit12: 0 Channel 0 POL is 0

* bit16: 0 Channel 0 data line is high level when idle

* bit20: 0 Channel 0 clock line is low level when idle

*/

base->CONFIGREG = 0; /* Set channel register */

/*

* ECSPI channel 0 settings, set the sampling period

* bit[14:0]: 0X2000 Sampling wait period, for example, when the SPI clock is 10MHz

* 0X2000 is equal to 1/10000 * 0X2000 = 0.8192ms, which is continuous

* The interval between each reading of data is 0.8ms

* bit15: 0 The sampling clock source is SPI CLK

* bit[21:16]: 0 Chip select delay, can be set to 0~63

*/

base->PERIODREG = 0X2000; /* Set sampling period register*/

/*

* SPI clock configuration of ECSPI, the SPI clock source comes from pll3_sw_clk/8=480/8=60MHz

* By setting PER_DIVIDER(bit[11:8]) and POST_DIVEDER(bit[15:12]) of CONREG register

* Divide the SPI clock source to get the SPI clock we want:

* SPI CLK = (SourceCLK / PER_DIVIDER) / (2^POST_DIVEDER)

* For example, if we want to set the SPI clock to 6MHz, then PER_DIVEIDER and POST_DEIVIDER are set as follows:

* PER_DIVIDER = 0X9.

* POST_DIVIDER = 0x0.

* SPI CLK = 60000000/(0X9 + 1) = 60000000=6MHz

*/

base->CONREG &= ~((0XF << 12) | (0XF << 8)); /* Clear the previous settings of PER_DIVDER and POST_DIVEDER*/

base->CONREG |= (0X9 << 12); /* Set SPI CLK = 6MHz */

}

/*

* @description: SPI channel 0 sends/receives one byte of data

* @param - base : SPI to use

* @param - txdata: data to be sent

* @return : None

*/

unsigned char spich0_readwrite_byte(ECSPI_Type *base, unsigned char txdata)

{

uint32_t spirxdata = 0;

uint32_t spitxdata = txdata;

/* Select channel 0 */

base->CONREG &= ~(3 << 18);

base->CONREG |= (0 << 18);

while((base->STATREG & (1 << 0)) == 0){} /* Wait for the transmit FIFO to be empty*/

base->TXDATA = spitxdata;

while((base->STATREG & (1 << 3)) == 0){} /* Wait for the receive FIFO to have data*/

spirxdata = base->RXDATA;

return spirxdata;

}