Design method for implementing UIP protocol stack on IP core 8051 microprocessor embedded in FPGA

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3.2 UIP workflow

The workflow of the TCP/IP protocol on the IP core 8051 embedded in the FPGA is actually a simplified workflow of the TCP/IP protocol, which is different from the formal TCP/IP protocol. The following workflow takes inputting a synchronization frame (ie: the first handshake of a three-way handshake) as an example. For UIP implemented by 8051, it is a passive connection establishment, and its correct output result should be the second handshake of the three-way handshake. Sending a confirmation synchronization frame is the expected result.


The following is a brief introduction to the entire workflow of UIP:

(1) Before the P0 port has data, read the data function and execute it repeatedly to monitor the P0 port (this situation is only during testing, in actual work, the physical layer notifies the reading function through a control signal whether there is data at the P0 port) ;

(3) is the 8th-level decomposed wavelet mode maximum value diagram of the signal; (4) is the high-frequency component of each level of the signal (a total of 9 levels), that is, the wavelet coefficient.


As can be seen from Figure 4, the fault signal analyzer can effectively collect real-time fault signals, and can effectively extract fault features after wavelet analysis of the signals, and the fault point location is obvious.


5 Conclusion

This portable catenary fault signal analyzer is developed and designed using the graphical programming language LabVIEW, which can realize high-speed real-time collection, online analysis, automatic storage, display and other functions of data. The high-speed digitizer NI PXI-5112 card has high sampling speed, stable and reliable performance, and is suitable for real-time monitoring of high-speed changing signals. The software is installed on the PXI-1042 industrial computer. It has the characteristics of small size, strong anti-interference ability, easy portability, etc. It also has the functions of fault nature judgment and fault location. The system is currently in operation at Shijiazhuang Substation with good results.


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Reference address:Design method for implementing UIP protocol stack on IP core 8051 microprocessor embedded in FPGA

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