Design method for implementing UIP protocol stack on IP core 8051 microprocessor embedded in FPGA

"introduction

As chips become larger and larger and resources become more abundant, the design complexity of chips also increases greatly. In fact, after the chip design is completed, some controls sometimes need to be changed according to the situation, which is often encountered during use. It would be very undesirable to change the chip design at this time, because designers need to participate in such changes, which is unacceptable to both designers and users. Therefore, it is necessary to make this simple control that can be changed exist during chip design, and at the same time, this change should be made relatively easy, relatively common, and as independent as possible from other design parts of the chip. In order to meet the above requirements, it is an ideal choice to embed an IP core in the FPGA, and the 8051 microprocessor is the best choice for this universal and simple-to-control IP core.

After the 8051 is embedded in the FPGA, a simple TCP/IP protocol can also be implemented on it to support remote access or remote debugging. This is just an application on the 8051 embedded in the FPGA. In order to ensure that users can implement different control operations on the 8051, an external flash can also be used to load the 8051 during design. In this way, the user only needs to add the compiled assembly language code to the flash to control the work of the 8051. At this time Users can achieve simple control without operating the FPGA at all, and all this requires is the keil compilation environment.

1 FPGA implementation of IP core 8051

There are many free 8051 cores available. These cores can be implemented through hardware description languages, and they can basically be synthesized, that is, they can be used directly. All that is needed is to make some simple modifications according to your specific needs. Can. Generally speaking, the transplantation of IP core 8051 is relatively simple.

The design and implementation of this system can use the mc8051 core of the oregano system, and add timing counting and serial port modules. The design structure block diagram of the 8051 microcontroller is shown in Figure 1.

In the FPGA design of the 8051 core, all functions including timing/counting, interrupts, serial ports, data and program memories, special registers, Boolean processing bit processors, etc. can be realized, and it is compatible with all instructions. It is only in the specific transplantation process. Just make some changes.

This method no longer distinguishes between internal and external program memory, because the internal storage capacity of the FPGA can already meet the requirements. At the same time, the capacity of the program memory is doubled (to 8KB) to meet the capacity requirements of large programs; in order to allow 8051 More powerful and versatile, it doubles the capacity of the data memory RAM to 256 bytes. It can be seen that the functions of 8051 have been enhanced during the design process, but this does not affect its control. It only expands the memory capacity in hardware, and this expansion only changes the width of the address line. , does not affect the correct execution of the 111 instructions at all. To the user this is just an increase in available internal RAM, no changes in control. Of course, when resources are tight and the program capacity is small, the memory capacity can also be reduced. This change is also quite convenient. You only need to change the width of the address line to achieve the purpose. It can be seen that the design of the IP core can be changed according to needs during design, and is not limited to 8051.

Although the entire 8051IP core can correctly execute all instructions and can realize serial port, timer and interrupt control, and the core working clock of the entire IP is also above 20 MHz, however, because all the instruction cycles at this time are not completely consistent with the real 8051 , Some instructions in the IP core require several more cycles to be executed than the real 8051, which complicates the analysis of the IP core's working clock, because there cannot be an accurate working clock comparison with the real 8051. However, after analysis, it can still be believed that the IP core should be able to work at around 15 MHz, which is about 15 times faster than the real 8051. This speed may be relatively low for the overall chip, but since this part has minimal logical correlation with other parts of the chip, it will not affect the overall performance of the chip. For some simple controls, this speed is still able to meet the requirements.

2 UIP protocol stack

2.1 Introduction to UIP

The main purpose of implementing the TCP/IP protocol in FPGA is to satisfy designers' remote debugging of the chip. In fact, meeting this requirement does not require very powerful and fast transmission capabilities. Too powerful functions will occupy too many resources, and in fact, many functions have no practical effect; at the same time, fast transmission speed is not required. After all, for the design of a chip, whether it is a design document or a design program, the capacity is very limited. After comprehensive consideration, you should choose a protocol that is simple to implement, takes up less resources, but can transmit data more stably. For this reason, this article chooses the relatively simple UIP protocol stack and abandons the more powerful LWIP protocol stack. Another advantage of choosing UIP is that this protocol stack is a TCP/IP protocol stack specially designed for microcontrollers such as microcontrollers. It can use the embedded IP core 8051 to implement the TCP/IP protocol without requiring additional logic units. .

UIP is characterized by a relatively small amount of code and data, so it can provide suitable implementation solutions for places where memory is tight, including the minimum implementation solution required by TCP/IP and only TCP, IP, ICMP (ping) and simple The UDP protocol, its specific implementation method is shown in Figure 2. In Figure 2, the mark with "×" indicates that it has been implemented.

2.2 Implementation method of UIP protocol stack

The four basic protocols of the TCP/IP protocol set can be implemented through UIP, including ARP Address Resolution Protocol, IP Internet Protocol, ICMP Network Control Message Protocol and TCP Transmission Control Protocol. In order to be applied on 8-bit and 16-bit processors, the UIP protocol stack adopts targeted methods when implementing protocols at each layer to ensure that the code size and memory usage are minimized.

When implementing the ARP address resolution protocol, in order to save memory, the ARP response packet can directly overwrite the ARP request packet; when implementing the IP network protocol, the original protocol is greatly simplified and fragmentation and reassembly are not implemented; when implementing When using the ICMP network control message protocol, only the echo service needs to be implemented. When UIP generates an echo message, it does not reallocate the memory space, but directly modifies the echo request message to generate an echo message. During design, the ICMP type field can be changed from "echo" to "echo re-ply" type, and the checksum can be recalculated and the checksum field modified. TCP in UIP does not implement a sliding window for sending and receiving data. The state of each TCP connection is saved by the uip_conn structure. The uip_conn structure includes information such as the local and remote TCP port numbers, the IP address of the remote host, the retransmission time value, the retransmission number of the previous segment, and the maximum size of the connection segment. The uip_conn structure array can be used to save all connections. The size of the array is equal to the maximum number of simultaneous connections that can be supported. In order to reduce memory usage, UIP does not cache the sent data packets when processing retransmissions. Instead, the application regenerates the sent data when retransmission is needed.

2.3 Interface of UIP protocol stack

In order for the UIP protocol stack to have maximum versatility, all protocol sets except the underlying hardware driver and top-level application layer can be "packaged" in a "library" during implementation. The protocol stack communicates with the underlying hardware and top-level applications through interfaces. In this way, uIP can be extremely versatile and independent, so that it can be transplanted to different systems and easily implement different applications, which well reflects the platform-independent characteristics of the TCP/IP protocol. The interface between the UIP protocol stack, the bottom layer of the system and the application program is shown in Figure 3. In the figure, each interface is implemented by a series of functions.

3 Implementation of UIP protocol stack on IP core 8051

3.1 Transplantation of UIP protocol stack on IP core 8051

Since the UIP protocol stack is specially written for microprocessors, transplantation is also very convenient, but the following points should be noted:

(1) The protocol stack is written in C language, so two header files need to be added during transplantation, one is the 8051 header file, and the other is the 8051 hardware initialization header file;

(2) When compiling through the keil c compiler, you need to pay attention when selecting the device. Only when the data register is selected to be 256 bytes can the compilation be successfully passed. This is why the data memory RAM of the previous 8051IP core needs to be expanded to 256 bytes. reason. If the RAM is not expanded, the error "Cannot write to the B9 address" will occur, because the B9 address does not exist before the RAM is expanded;

(3) Send the hex file generated by software keil compilation into the program memory of 8051 to implement a simple TCP/IP protocol on the IP core 8051. This will be different during software testing and actual work. During software testing, the hex file needs to be used as the initialization input of the program memory. That is, when the EDA software compiles 8051, the path of the initialization file mif of the program memory is set to the path where hex is located. After the comprehensive wiring is completed, the content of the hex file is entered. program memory. In this way, the TCP/IP protocol can be implemented on the 8051IP during simulation.