s3c2440 value migration u-boot-2016.03 Part 6 supports mtd yaffs programming

1. Solve the startup error
Warning - bad CRC, using default environment.
Search found in /tools/env/fw_env.c
/* Place it in NAND FLASH with a size of 128K starting address */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
#define CONFIG_ENV_OFFSET (256<<10)
#define CONFIG_ENV_SIZE CONFIG_SYS_ENV_SECT_SIZE

2, add MTD
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define MTDIDS_DEFAULT " nand0=nand"
# define MTDPARTS_DEFAULT "mtdparts=nand:256k(uboot),"
"128k(env),"
"2m(kernel),-(fs)"

Add run_command("mtdparts default", 0); in /common/board_r.c
man_loop ;

Erase nand flash
nand erase.part uboot
nand write 0x30000000 uboot

3, download test

nfs 0x300000000 192.168.1.10:nfs/fs.yaffs2
NAND ERASE.PART FS NAND
WRITE.YAFFS 0x30000000 0x00260000 0x8607c0 (File size)
Set Bootargs Noinitr =/DEV/MTDB lock3 init =/linuxrc console = ttysac0
boot start

Writing error
Unknown nand command suffix '.yaffs2'

4. Support yaffs2.

I found one in smdk2440.h. After configuring #define CONFIG_YAFFS2

and compiling, it is much larger, 335K, and the menu has several more functions
yls - yaffs ls
ymkdir - YAFFS mkdir
ymount - mount yaffs
ymv - YAFFS mv
yrd - read file from yaffs
yrdm - read file to memory from yaffs
yrm - YAFFS rm
yrmdir - YAFFS rmdir
ytrace - show/set yaffs trace mask
yumount - unmount yaffs
ywr - write file to yaffs
ywrm - write file from memory to yaffs

I tried to mount it, but it failed and the document was not found. As a result, u-boot was also very large. Try another method.

You can use #define CONFIG_CMD_NAND_YAFFS before.
Comparing u-boot 2013, 2014 and 2015, this function is available, but it has been removed from 2015-10.
Refer to u-boot 2015 to modify the code to add support
/* Add compatible yaffs2 burning support */
/include/configs /smdk2440.h
#define CONFIG_CMD_NAND_YAFFS
/cmd/nand.c
in 543line:
if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
add inside 622line:
#ifdef CONFIG_CMD_NAND_YAFFS
} else if (!strcmp(s, ".yaffs")) {
if (read) {
printf("Unknown nand command suffix '%s'.n", s);
return 1;
}
ret = nand_write_skip_bad(nand, off, &rwsize, NULL,
maxsize, (u_char *)addr,
WITH_YAFFS_OOB);
#endif

/include/nand.h 101line: Add
#define WITH_YAFFS_OOB (1 << 0) /* whether write with yaffs format. This flag * is a 'mode' meaning it cannot be mixed with * other flags */

/drivers/mtd/nand/nand_util.c 583line:
#ifdef CONFIG_CMD_NAND_YAFFS
if (flags & WITH_YAFFS_OOB) {
if (flags & ~WITH_YAFFS_OOB)
return -EINVAL;

int pages;
pages = nand->erasesize / nand->writesize;
blocksize = (pages * nand->oobsize) + nand->erasesize;
if (*length % (nand->writesize + nand->oobsize)) {
printf("Attempt to write incomplete page"
" in yaffs moden");
return -EINVAL;
}
} else
#endif

666line:
#ifdef CONFIG_CMD_NAND_YAFFS
if (flags & WITH_YAFFS_OOB) {
int page, pages;
size_t pagesize = nand->writesize;
size_t pagesize_oob = pagesize + nand->oobsize;
struct mtd_oob_ops ops;

ops.len = pagesize;
ops.ooblen = nand->oobsize;
ops.mode = MTD_OPS_AUTO_OOB;
ops.ooboffs = 0;

pages = write_size / pagesize_oob;
for (page = 0; page < pages; page++) {
WATCHDOG_RESET();

ops.datbuf = p_buffer;
ops.oobbuf = ops.datbuf + pagesize;

rval = mtd_write_oob(nand, offset, &ops);
if (rval != 0)
break;

offset += pagesize;
p_buffer += pagesize_oob;
}
}
else
#endif
{
The following parts should be included here. Finally, after u-boot is modified, there will be a big patch. You can download and compare.
............
}
After compilation, 252K
re-programming error
NAND write to offset 2a1000 failed -22 0 bytes written: ERROR
ops.mode = MTD_OPS_RAW; This also needs to be changed.

It's finally completed. You can program yaffs2, and you can also use NAND FLASH NOR FLASH, network card, and u-boot. It's almost over.

2016.03.u-boot patch

   1 diff -urN u-boot-2016.03/arch/arm/cpu/arm920t/init.c u-boot-2016.03ok/arch/arm/cpu/arm920t/init.c

   2 --- u-boot-2016.03/arch/arm/cpu/arm920t/init.c    1970-01-01 07:00:00.000000000 +0700

   3 +++ u-boot-2016.03ok/arch/arm/cpu/arm920t/init.c    2016-05-19 05:34:00.645377559 +0800

   4 @@ -0,0 +1,206 @@

   5 +/* NAND FLASH controller */

   6 +#define NFCONF (*((volatile unsigned long *)0x4E000000))

   7 +#define NFCONT (*((volatile unsigned long *)0x4E000004))

   8 +#define NFCMMD (*((volatile unsigned char *)0x4E000008))

   9 +#define NFADDR (*((volatile unsigned char *)0x4E00000C))

  10 +#define NFDATA (*((volatile unsigned char *)0x4E000010))

  11 +#define NFSTAT (*((volatile unsigned char *)0x4E000020))

  12 +

  13 +/* CLK */

  14 +#define CLKDIVN  (*(volatile unsigned long *)0x4C000014)

  15 +#define MPLLCON  (*(volatile unsigned long *)0x4C000004) 

  16 +

  17 +/* SDRAM */

  18 +#define BWSCON    (*(volatile unsigned long *)0x48000000) 

  19 +#define BANKCON4  (*(volatile unsigned long *)0x48000014) 

  20 +#define BANKCON6  (*(volatile unsigned long *)0x4800001c) 

  21 +#define REFRESH   (*(volatile unsigned long *)0x48000024) 

  22 +#define BANKSIZE  (*(volatile unsigned long *)0x48000028) 

  23 +#define MRSRB6    (*(volatile unsigned long *)0x4800002c)

  24 +

  25 +void init_clock(void)

  26 +{

  27 +    //Mpll = 400M

  28 +    MPLLCON = (0x5c<<12) | (1<<4) | 1;

  29 +    //FCLK 400M HCLK 100M PCLK 50M

  30 +    CLKDIVN = 2<<1 | 1<<0;

  31 +    __asm__(

  32 +        "mrc  p15,0,r0,c1,c0,0n" 

  33 +        "orr  r0,r0,#0xc0000000n"

  34 +        "mcr  p15,0,r0,c1,c0,0n" 

  35 +    );

  36 +}

  37 +

  38 +void init_sdram(void)

  39 +{

  40 +    #if 0

  41 +    BWSCON   = 1<<25;

  42 +    BANKCON6 = 1<<16 | 1<<15 | 1;

  43 +    REFRESH  = (1<<23) + 1268;

  44 +    BANKSIZE = 1<<7 | 1<<4 | 1;

  45 +    MRSRB6   = 0x30;

  46 +    #else

  47 +    BWSCON   = 1<<25 | 1<<16;

  48 +    BANKCON4 = 0x00000740;

  49 +    BANKCON6 = 1<<16 | 1<<15 | 1;

  50 +    REFRESH  = (1<<23) + 1268;

  51 +    BANKSIZE = 1<<7 | 1<<4 | 1;

  52 +    MRSRB6   = 0x30;

  53 +    #endif

  54 +}

  55 +

  56 +void clear_bss(void)

  57 +{

  58 +    extern int __bss_start, __bss_end;

  59 +    int *p = &__bss_start;

  60 +    

  61 +    for (; p < &__bss_end; p++)

  62 +    {    

  63 +        *p = 0;

  64 +    }

  65 +}

  66 +

  67 +static void nand_latency(void)

  68 +{

  69 +    int i=100;

  70 +    while(i--);

  71 +}

  72 +

  73 +static void nand_is_ready(void)

  74 +{

  75 + //bit 0 : 1 Not busy anymore

  76 +    while(! (NFSTAT & 1));

  77 +}

  78 +

  79 +static void nand_write_addr(unsigned int addr)

  80 +{

  81 +    int col, page;

  82 +    col = addr % 2048;

  83 +    page = addr / 2048;

  84 +    

  85 +    NFADDR = col & 0xff;            /* Column Address A0~A7 */

  86 +    nand_latency();        

  87 +    NFADDR = (col >> 8) & 0x0f;     /* Column Address A8~A11 */

  88 +    nand_latency();

  89 +    NFADDR = page & 0xff;            /* Row Address A12~A19 */

  90 +    nand_latency();

  91 +    NFADDR = (page >> 8) & 0xff;    /* Row Address A20~A27 */

  92 +    nand_latency();

  93 +    NFADDR = (page >> 16) & 0x03;    /* Row Address A28~A29 */

  94 +    nand_latency();

  95 +}

  96 +

  97 +static unsigned char nand_read_char(void)

  98 +{

  99 + //Only keep 8 bits

 100 +    return NFDATA & 0xff;

 101 +}

 102 +

 103 +static void nand_cmd(unsigned char cmd)

 104 +{

 105 +    NFCMMD = cmd;

 106 +    nand_latency();

 107 +}

 108 +

 109 +static void nand_select_chip(void)

 110 +{

 111 + //1bit : 0 selected

 112 +    NFCONT &= ~(1<<1);

 113 +}

 114 +

 115 +static void nand_deselect_chip(void)

 116 +{

 117 + //1bit : 1 selected

 118 +    NFCONT |= (1<<1);

 119 +}

 120 +

 121 +static void nand_reset(void)

 122 +{

 123 +    nand_select_chip();

 124 +    nand_cmd(0xff);

 125 +    nand_deselect_chip();

 126 +}

 127 +

 128 +void nand_init_ll(void)

 129 +{    

 130 + //TACLS 12ns at 3.3v

 131 +    #define TACLS   0

 132 +    //12ns

 133 +    #define TWRPH0  1

 134 +    //5ns

 135 +    #define TWRPH1  0

 136 +    NFCONF = TACLS<<12 | TWRPH0<<8 |  TWRPH1<<4;

 137 + /* 4 EXC

 138 + * 1 CE Do not select it now, select it when you use it

 139 + * 0 Start flash controller

 140 +     */

 141 +    NFCONT = 1<<4 | 1<<1 | 1;

 142 +    nand_reset();

 143 +}

 144 +

 145 +static void nand_read(unsigned int addr, unsigned char *buf, int len)

 146 +{

 147 + //selected

 148 +    nand_select_chip();

 149 + //j address may not be read starting from 0 alignment

 150 +    unsigned int i = addr,j = addr % 2048;

 151 +    for(; i<(addr + len);)

 152 +    {

 153 + //read command

 154 +        nand_cmd(0x00);

 155 +        nand_is_ready();

 156 +        

 157 + //Sending address

 158 +        nand_write_addr(i);

 159 +        nand_is_ready();

 160 +    

 161 + //Issue read command now

 162 +        nand_cmd(0x30);

 163 +        nand_is_ready();

 164 + //Read 2K

 165 +        for(; j<2048; j++)

 166 +        {

 167 +            *buf = nand_read_char();

 168 +            buf++;

 169 +            i++;

 170 +        }

 171 +        j=0;

 172 +        nand_latency();

 173 +    }

 174 + //Uncheck

 175 +    nand_deselect_chip();

 176 +}

 177 +

 178 +static int boot_is_nor()

 179 +{

 180 + //Use the characteristics of NOR that cannot be written to judge

 181 +    volatile unsigned int *p = (volatile unsigned int *)0;

 182 +    unsigned int val;

 183 + val = *p;

 184 +    *p = 0x12345678;

 185 +    if(0x12345678 == *p)

 186 +    {

 187 + *p = val;

 188 +        return 0;

 189 +    }

 190 +    return 1;

 191 +}

 192 +

 193 +//The on-chip 4K program needs to be copied to the linked SDRAM

 194 +void copy_code_to_sdram(unsigned char *src,unsigned char *dst,int len)

 195 +{

 196 +    int i = 0;

 197 +    if(boot_is_nor())

 198 +    {

 199 +        while(i < len)

 200 +        {

 201 +            dst[i] = src[i];

 202 +            i++;

 203 +        }

 204 +    }

 205 +    else

 206 +    {

 207 +        nand_read((int)src, dst, len);

 208 +    }

 209 +}

 210 +

 211 diff -urN u-boot-2016.03/arch/arm/cpu/arm920t/Makefile u-boot-2016.03ok/arch/arm/cpu/arm920t/Makefile