(3) Byte format, clock synchronization and arbitration of I2C bus

Byte format

Each byte sent to the SDA line must be 8 bits. The number of bytes per transfer is unlimited. Each byte must be followed by an ACK response bit. Data is transferred starting with the most significant bit (MSB) .If the slave needs to perform some function before it can receive or send new complete data, such as servicing an internal interrupt, then it can pull the clock line SCL low to force the master to enter the wait state. When the slave is ready for the new word During data transmission, the clock line SCL is released and data transmission continues.

ACK and NACK

An ACK occurs after each byte. The ACK acknowledge bit allows the receiver to notify the transmitter that the byte was successfully received and the next byte can be sent. The host generates all clock pulses, including the 9th clock pulse for the acknowledge bit.

The ACK response signal is defined as follows: the transmitter releases the SDA line in the 9th clock pulse of ACK, so the receiver can pull SDA low so that SDA is guaranteed to be low during the high level of this clock pulse. Establish and hold time should also be calculated.

When SDA is still high during the 9th clock pulse, it is defined as a NACK signal. At this time, the host can generate a stop condition to terminate the transfer, or a repeated start condition to start a new transfer. There are 5 situations Leading to the generation of NACK:

1. There is no receiver on the current transmission address of the bus, so no device responds with ACK.

2. Because the receiver is processing some real-time functions and has not yet prepared to communicate with the host, the receiver cannot send or receive.

3. During transmission, the recipient receives unrecognizable data or commands.

4. During transmission, the receiver cannot receive more data bytes.

5. The master-receiver shall notify the slave-sender of the end of the transmission.

Clock synchronization

On an idle bus, two masters can start transmission at the same time, so there must be a way to decide which master will control the bus and complete its data transmission. This method is clock synchronization and arbitration. In a single-master system, clock synchronization and arbitration are not Needed.

Clock synchronization is achieved by using a wire-AND connection with the SCL line using the I2C interface. Meaning that the period when the SCL line goes from high to low will cause the host to start counting its low periods, and once the host clock goes low, it will keep the SCL line in this state. state until the clock reaches a high level. However, if another clock is still low, the change of the clock from low to high does not change the state of the SCL line. The time SCL is pulled low is determined by the longest low period Decision. The host with a shorter low-level period enters the HIGH wait-state at this time.

When the low-level periods of all hosts have ended, the clock line returns to high level. At this time, the status of the host clock and SCL is consistent, and all hosts begin to count their high-level periods. The first one to end the high-level period The host pulls the SCL line low again.

In this case, the low-level period of the synchronized SCL clock is determined by the longest low-level period among all hosts, and the high-level period is determined by the shortest high-level period.

arbitration

Arbitration, like synchronization, is part of the protocol requirements when there is more than one master in the system. The slave does not participate in the arbitration process. The master can start a transfer only when the bus is free. Two masters may start a transfer as specified by the start condition. A start condition is generated within the minimum hold time (tHD; SDA), and a valid start condition is generated on the resulting bus. At this time, arbitration is needed to decide which host completes its transmission.

The arbitration process is performed bit by bit. In each bit, when SCL is high, each host checks to see if the level of SDA matches the level it sends. This process may last for many bits. As long as The transmission is the same, then the two hosts can complete the complete transmission without error. When a host tries to send high, but detects that SDA is low, then the host knows that it has lost arbitration and turns off its own SDA output. The other host will complete its transmission.

No information is lost during the arbitration process. A master that loses arbitration generates a clock pulse at the end of the byte in which it lost arbitration and must restart its transmission when the bus becomes free.

If a master contains slave functionality and it loses arbitration during the addressing phase, then the master that wins arbitration may address it. The master that loses arbitration must immediately switch to its slave mode.

The figure below shows the arbitration processing of the two hosts. When the actual level values ​​of the DATA1 and SDA lines generated by the host are different, the output of DATA1 is turned off. Host 1 loses the arbitration. The transmission of host 2 that won the arbitration Data is not affected.

Because the I2C bus is controlled by addresses only and data is sent only by the master that wins arbitration, there is no overriding master and there is no priority order on the bus.

When the arbitration process is in progress, one host sends repeated start conditions or termination conditions while the other host is still sending data, then there is an undecided state. In other words, this situation will occur under the following conditions :

Host 1 sends a repeated start condition, Host 2 sends a data bit

Host 1 sends a termination condition, Host 2 sends a data bit

Host 1 sends a repeated start condition, Host 2 sends a stop condition