Remote upgrade of terminal system program based on LPC2124 chip and GPRS network

The on-site power monitoring terminal is an intelligent device that measures simultaneously with multi-functional metering equipment and monitors power usage in an all-round way. In the current national power shortage, it plays the role of peak shaving and valley filling, and improves the operating efficiency of the power grid. It is especially suitable for power monitoring of large power consumers.

Market demand and the maturity of application technology are often contradictory. Users always hope to use products with complete functions and advanced technology as soon as possible, but there is always a process from new technology to application. The length of this process determines the market prospects of the product to the greatest extent. If you want to grasp the market well, you often have to develop the market while improving the technology. Practice is the only criterion for testing truth. To make a good product, you must form an interactive relationship with users and use user feedback to continuously improve the product. In addition, after the product is used for a long time, flaws in the terminal program design will slowly surface, which requires the terminal system program to be upgraded. If on-site ISP upgrades are performed on hundreds of terminals, it will not only waste a lot of manpower and financial resources, but more importantly, waste valuable time, delay market development opportunities, and reduce users' credibility for the product.

In the era of rapid development of the Internet, connecting terminals to the Internet is a reliable and realistic solution to the above problems. This design solution is applied to power on-site monitoring terminals, using high-performance Philips ARM MCULPC2124, combined with GPRS technology to achieve remote upgrade of terminal system programs.

1 Introduction to LPC2124 chip

1.1 Function introduction

LPC2124 is based on a 16/32-bit ARM7TDMI-SCPU that supports real-time simulation and tracking, and has 236 KB of embedded high-speed Flash memory and 16 KB of RAM. For embedded flash memory, it supports JTAG, ISP, IAP and other programming methods.

LPC2124 has a very small 64-pin package, extremely low power consumption, multiple 32-bit timers, 4-channel 10-bit ADC, PWM output, 46 GPIOs and up to 9 external interrupts, and has built-in wide range of serial communication interface, making them particularly suitable for industrial control. Because power consumption monitoring terminals have high requirements on hardware resources, complex software functions, and strong real-time performance, the use of LPC2124 can improve the cost performance of the product.

1.2 Flash storage system

The LPC2124 storage system contains 17 sectors of 256 KB. The Flash memory starts from the O address and increases upwards. The sizes of the 17 sectors are also distributed continuously. The total capacity of the 17 sectors is 248 KB. The remaining 8 KB storage space is the Boot sector. The Boot sector is located at the top of the Flash storage system, and the address space is 0x0003 EO00~0x0003FFFF. The address allocation of the LPC2124 storage system is shown in Figure 1.

Boot Block occupies the 17th sector, which is the Boot sector. The storage space of this sector is specially used to store the B00t loader, control the initialization operation after reset, and provide Flash programming method (code). The B00t loader enables programming of blank slices, erasing and reprogramming of programmed devices, and programming of Flash memory by applications in a running system.

1.3 Programming of Flash storage system

LPC2124 supports multiple ways to program Flash to write user code or data. The first is through the built-in serial JTAG interface; the second is through UART0 for in-system programming (ISP); the third is through in-application programming (IAP).

1.3.1 JTAG programming

The JTAG Flash programming of LPC2124 can easily download programs to the on-chip Flash, but the JTAG interface is more important to provide hardware system debugging functions, such as realizing software breakpoints and single steps. JTAG Flash programming requires interrupting the normal operation of the application software, requiring more connections, shorter communication distance, and requiring on-site programming. It is only suitable for debugging and use of products during the development period.

1.3.2 In-system programming

ISP (In-Svstam Programming) technology, that is, in-system programmable technology, means that blank devices on the circuit board can be programmed to write end-user code without removing the device from the circuit board; programmed devices can also be used in ISP mode Erase or reprogram. LPC2124 supports ISP Flash programming, but to prevent the normal operation of the application software, it needs to provide certain hardware resources + including UARTO port, RS232 driver and CPU special pin status; programming requires on-site operation, very suitable for portable intelligent instruments upgrade, but it is obviously not suitable for equipment with special installation environment such as power monitoring terminals. For details on ISP programming principles, please refer to the reference literature.

1.3.3 In-application programming

In-Application Programming (IAP) is a programming mode applied to F1ash program memory. Simply put, it is to read, erase or write a certain section of the program's storage space under the control of the application program. Very similar to ISP operation. It has online programming function and overcomes the shortcomings of ISP. It can read/write operations on another program Flash when the application program is running normally, and can even control the read/write operations on a certain segment, a certain page or even a certain byte. This brings great flexibility for data storage and field upgrades of firmware.

2 Hardware design of IAP function

Based on the analysis of the above three programming methods of LPC2124, IAP implementation is naturally the best choice for terminal program upgrade. The following introduces a remote IAP system solution based on GPRS. The system block diagram is shown in Figure 2.

AT45DB08081B, 8Mb serial flash memory, has the power-down data storage of ROM and the read/write speed of RAM. It supports the fastest clock frequency of 20MHz and the number of erases and writes up to 10,000 times. It has two built-in 264-byte SRAM buffers, making it Programming of the main memory bank can be performed continuously, eliminating programming waiting time. AT45DB081B adopts CASON-8 package, supports 2.5~3.6 V low voltage, low operating power consumption, supports mode O and 3 SPI bus interface, simple interface with MCU, stable and reliable, very suitable for digital voice, image, program code and data storage applications. In this design, mode 0 is used to communicate with LPC2124, and the speed can reach 1/8 of the main frequency of the MCU.

The GPRS module uses the Q2406B produced by Wavecom Company, a dual-frequency GPRS/GSM module (EGSM900/1800 MHz or EGSM900/1900 MHz), with built-in TCP/IP, fully compatible with standard AT commands; its design and development comply with the ETSI GSM Phase 2+ standard.

3 Software design of IAP function

3.1 IAP programming interface

The IAP program of LPC2124 is located in the Boot sector. After reset, the entire Bool sector is mapped to the storage address Ox7FFFFE000~Ox7FFFFFFF; the entry address of the IAP is 0x7FFFFFFFo, and the program is Thumb code. IAP programming commands use the top 32 bytes of RAM, so applications should reserve this portion of RAM. During erase/program operations using IAP, the on-chip Flash memory is inaccessible. When the user application is running, the interrupt vector in the user F1ash area is valid, so before calling the Flash erase/write IAP, the user should disable interrupts or ensure that the user interrupt vector is valid in RAM and the interrupt handler is located in RAM. The IAP code does not use or disable interrupts.

3.2 IAP programming C language implementation

For in-application programming, LPC2124 calls the IAP program by pointing the word pointer in register R0 to the memory (RAM) containing the command code and parameters. The result of the IAP command is returned to the memory (RAM) pointed to by register R1.

The following C language code can be used to call the IAP of LPC2124:

◆Define the IAP program entry address

#definc lAP_LOCATl0N Ox7FFFFFFFl

◆Define data structures to pass IAP command tables and results to IAP programs

unslgned long Command［5］;

unsigncd long Result［2］;

◆Define function type pointer. The function includes two parameters and no return value.

typcdef void(*IAP)(unsigned int[], unsigncdim int[]);

IAP iap_entry; //Define function pointer

◆Set function pointer

iap_entry=(IAP)IAP_LOCATION;

◆Use the following statement to call IAP

iap_entry(command,result);

This system is transplanted based on the LPC2124 project template. On the ADSl.2 embedded software development platform, C language is used to directly call the IAP program code to implement IAP programming. For detailed explanations of IAP command codes, status codes and commands, as well as detailed applications of IAP functions, see the reference literature.

4 Application of remote upgrade in on-site power monitoring terminal

The design of the terminal software system includes the design of the user boot program (different from the Boot loader, the former is designed by the user, and the latter is designed and solidified by the chip manufacturer) and the design of the application program. Their entry addresses in LPC2124 are different. After the terminal is reset, if it does not enter the ISP programming state, the user boot program will be executed first, and the user boot program will decide whether to perform IAP upgrade or run normally; the application implements various functions of the terminal, including new Download version application upgrade package.

4.1 End-user boot program design

The end-user boot program is designed based on the idea of ​​a file system. The terminal application code is stored in the Flash memory of LPC2124. When the terminal is running normally, the MCU continuously reads instructions from the Flash. If the application is upgraded, that is, the Flash memory sectors occupied by the application are erased and reprogrammed, obviously the Flash sectors occupied by the code that performs Flash programming cannot be erased, so the code of the upgrade program can only use separate sectors. Storage area, the execution of the upgrade program can be called by the application program or executed as a separate program. Since the IAP code of LPC2124 uses the 16-bit Thumb instruction set, interrupts should be disabled or turned off during the execution of IAP. If the upgrade program is designed in the form of application calls, it will increase the complexity of the application design and make the upgrade less reliable. After the LPC2124 is reset, since the Boot program always reads instructions from the 0 address of the Flash, the upgrade program code is placed in the start sector and is designed to be part of the user boot program, and the user boot program is always unmodified. If the upgrade process fails, the application can be re-upgraded after the MCU is reset, which enhances the reliability of the upgrade.