Detailed explanation of the internal PLL0 principle and application design of LPC1754

LPC175x, as the cortex-M3 core chip mainly promoted by NXP, is widely used in various industrial control, electronic metering, alarm systems and other fields. Regardless of the application, it is essential to select the appropriate clock source according to actual needs and configure a reasonable system clock frequency. Less.

Oscillator

Taking the EasyARM-1754M3 development board as an example, the LPC1754 chip external crystal oscillator contains two, an external high-speed crystal oscillator with a frequency of 12MHz and an external low-speed crystal oscillator with a frequency of 32.768KHz. Both can be selected or not selected using software settings. In addition, LPC1754 also contains three independent oscillators, which are the internal main oscillator, the internal RC oscillator and the internal RTC oscillator. Commonly used oscillators in practical applications are external high-speed crystal oscillators and external low-speed crystal oscillators.

Introduction to the internal PLL0 principle of LPC1754

PLL0 contains multiple registers, among which the selection of the PLL0 clock source can be set in the CLKSRCSEL register. PLL0 multiplies the input clock, and then divides the frequency to provide a real-time clock signal for the CPU and chip peripherals. PLL0 can generate a clock frequency of up to 100MHz, which is the maximum allowed by the CPU.

The internal structure of PLL0 can be represented as the following figure. The output clock signal of PLL0 is pllclk, which is divided by the CPU clock divider to generate a system clock. The system clock then enters the peripheral clock divider and outputs multiple peripherals. clock.

Application examples

All routines provided with the EasyARM-1754M3 development board use the unified system initialization function SystemInit() to configure the system clock to 96MHz and the peripheral clock to the default value of 24MHz. Users can modify the parameters according to their actual needs under the condition that they have a certain understanding of this function. Modifiable items generally include three important parameters: clock source, frequency multiplication coefficient, and distribution coefficient. The PLL0 configuration in the system initialization function Part of the program listing is shown below:

#if (CLOCK_SETUP) /* Clock Setup */

LPC_SC->SCS = SCS_Val;

if (SCS_Val & (1 << 5)) {                                   /* If Main Oscillator is enabled  */

while ((LPC_SC->SCS & (1<<6)) == 0);                     /* Wait for Oscillator to be ready*/

}

LPC_SC->CCLKCFG = CCLKCFG_Val; /* System clock frequency division value, CCLKCFG_Val value can be changed*/

LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */

LPC_SC->PCLKSEL1 = PCLKSEL1_Val;

LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select clock source, CLKSRCSEL_Val value can be changed*/

#if (PLL0_SETUP)

LPC_SC->PLL0CFG = PLL0CFG_Val; /*PLL0 frequency multiplication value, PLL0CFG_Val value can be changed*/

LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */

LPC_SC->PLL0FEED = 0xAA;

LPC_SC->PLL0FEED = 0x55;

while (!(LPC_SC->PLL0STAT & (1<<26)));                    /* Wait for PLOCK0               */

LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */

LPC_SC->PLL0FEED = 0xAA;

LPC_SC->PLL0FEED = 0x55;

#endif

LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */

LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */

#endif

The key parameters are the PLL0 frequency multiplication coefficient PLL0CFG_Val and the CPU clock frequency division coefficient CCLKCFG_Val. Since the register value is 1 smaller than the actual value, their actual values ​​are 16 and 4. In addition, every time you want to write a new value to the PLL0 related register, you need to write the feed series into the feed register before it can take effect. Usually, 0xAA and 0x55 are written into the PLLxFEED register one after another.

After preparing the relevant parameters, you must determine the selected clock source based on the parameter configuration, and calculate the final system clock frequency. Under the condition that the external 12MHz clock source is selected, the program will jump to the position of CASE1 to run, and combined with the previously given parameters, the system clock frequency CCLK=12M×2×16/1/4=96MHz is calculated.

case 1: /* Main oscillator => PLL0 */

SystemFrequency = (OSC_CLK *

((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / /*The lower 15 bits of PLL0STAT are 15, the multiplication value*/

(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / /*Bit 16~23 of PLL0STAT is 0, frequency division value*/

((LPC_SC->CCLKCFG & 0xFF)+ 1)); /*CCLKCFG is the system frequency division value, 3 */

break;

Another example is to use a 32.768KHz external low-speed crystal oscillator as the clock source and also generate a 96MHz system clock. Just change CLKSRCSEL_Val, CCLKCFG_Val, and PLL0CFG_Val to 0x02, 0x02, and 0x1127 (4391) respectively, which means to select an external low-speed crystal oscillator. , the system frequency division is 3 (the register value is 1 less than the actual value), the PLL0 frequency division value is 4392 (the PLL0 frequency division value is not set, the default is 0), calculation: 32.768×2×4392÷3=95944.704KHz,

About 96MHz.

Clock configuration considerations

During the entire code writing process, special attention must be paid to the operation of the feed register PLLxFEED, and the order of writing 0xAA and 0x55 must be strictly followed. In addition, make sure that no interrupt service routine occurs when executing the write feed sequence. That is, when executing the PLL0 feed operation, interrupts must be disabled. If the written value is incorrect, or the conditions for no interrupt occurrence are not met, then the No changes to the PLL0CFG register will take effect.

When configuring the required system clock frequency according to your own needs, you often use the Debug function of the emulator to observe relevant parameters to verify whether the clock frequency configuration is correct. However, you cannot set any breakpoints when executing the PLL0 feed operation, otherwise the configuration will not take effect.