How to write the interrupt vector of s3c2440 bare metal (2)

Let’s first explain the LDR pseudo-instruction.

The LDR pseudo-instruction reads a 32-bit constant or an address value into a register.

Syntax format

LDR{cond} register,={expr|label-expr}

The symbols and parameters are explained as follows:

●cond is an optional instruction execution condition.

●register is the target register.

●expr is a 32-bit constant. The compiler will process the LDR pseudo-instruction as follows based on the value of expr.

●When the address value represented by expr does not exceed the value range of the address in the MOV or MVN instruction, the compiler uses the appropriate MOV or MVN instruction to replace the LDR pseudo-instruction.

●When the address represented by expr exceeds the value range of the address in the MOV or MVN instruction, the compiler places the constant in the data buffer and reads the constant with a PC-based LDR instruction.

●label-expr is a PC-based address expression or an external expression. When label-expr is a PC-based address expression, the compiler places the value represented by label-expr in the data buffer and reads the value with a PC-based LDR instruction. When label-expr is an external expression, or an expression other than the current section, the assembly compiler will insert a link relocation pseudo-operation in the target file, so that the linker will generate the address during linking.

Use LDR pseudo-operation to write the interrupt vector table as follows:

/* The second way to write the interrupt vector table */
ldr pc ,= reset
ldr pc ,= undefined_instruction
ldr pc ,= software_interrupt
ldr pc ,= prefetch_abort
ldr pc ,= data_abort
ldr pc ,= not_used
ldr pc ,= irq
ldr pc ,= fiq

reset:
	b reset
undefined_instruction:
	b undefined_instruction
software_interrupt:
	b software_interrupt
prefetch_abort:
	b prefetch_abort
data_abort:
	b data_abort
not_used:
	b not_used
irq:
	b q
fiq:
	b fiq

The disassembly results are as follows:

33f80000 <.text>:
33f80000: e59ff038 ldr pc, [pc, #56]; 33f80040 <.text+0x40>
33f80004: e59ff038 ldr pc, [pc, #56]; 33f80044 <.text+0x44>
33f80008: e59ff038 ldr pc, [pc, #56]; 33f80048 <.text+0x48>
33f8000c: e59ff038 ldr pc, [pc, #56]; 33f8004c <.text+0x4c>
33f80010: e59ff038 ldr pc, [pc, #56]; 33f80050 <.text+0x50>
33f80014: e59ff038 ldr pc, [pc, #56]; 33f80054 <.text+0x54>
33f80018: e59ff038 ldr pc, [pc, #56]; 33f80058 <.text+0x58>
33f8001c: e59ff038 ldr pc, [pc, #56]; 33f8005c <.text+0x5c>
33f80020: eafffffe b 33f80020 
33f80024: eafffffe b 33f80024 
33f80028: eafffffe b 33f80028 
33f8002c: eafffffe b 33f8002c 
33f80030: eafffffe b 33f80030 
33f80034: eafffffe b 33f80034 
33f80038: eafffffe b 33f80038 
33f8003c: eafffffe b 33f8003c 
33f80040: 33f80020 mvnccs r0, #32; 0x20
33f80044: 33f80024 mvnccs r0, #36; 0x24
33f80048: 33f80028 mvnccs r0, #40; 0x28
33f8004c: 33f8002c mvnccs r0, #44; 0x2c
33f80050: 33f80030 mvnccs r0, #48; 0x30
33f80054: 33f80034 mvnccs r0, #52; 0x34
33f80058: 33f80038 mvnccs r0, #56; 0x38
33f8005c: 33f8003c mvnccs r0, #60; 0x3c

It can be seen that after the LDR pseudo-instruction is compiled by the compiler, the address constant is stored at the end of the code segment and accessed using the address relative to the PC offset. Among them, the address constant is fixed 0x33f80020..., that is, the address of the symbol has been determined during the link stage.

When the code is running at address 0 (before relocation), this instruction will point the PC to the runtime address. At this time, there is no instruction at the runtime address, so an error will occur. Therefore, LDR register,=label-expr is address-related.