Registers involved in 5 interrupts of Qingxiang 51 microcontroller

The timer counts on-chip clock pulses, and the counter counts external pulses.

The 51 microcontroller has two 16-bit timers/counters: timer 0P3.4 and timer 1 P3.5

3.0 RXD serial port input

3.1TXD

3.2 External interrupt 0

3.3 External interrupt 1

3.4 T0

3.5 T1

3.6 WR external write control

3.7 RD external read control

We know the clock cycle of the microcontroller through the crystal oscillator frequency, and then multiply it by 12 to get the machine cycle. Each machine cycle adds 1 to the register until an overflow occurs and an interrupt is generated.

100MHZ

Period=1/frequency t=1/100M=10^-8(s)=10ns

1. In the timing mode, every time a machine cycle passes, the counter value increases by one, and overflows when the register is full.

The maximum single timing time is 65535*1.085us

2. In counting mode P3.4 P3.5, the counting register increases by one every time a pulse comes.

TCON (timing control register)----start timing counter (bit addressable)

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TF1: T1 overflow flag, set by hardware when the timer counter overflows.

TR1: Timer TI operation control bit, equal to 1 to allow counting

IE0/1: External interrupt request flag. 0 – No application

IT0/1: Trigger mode selection bit for external interrupt request. 0—effective at low level 1—effective at negative transition

TMOD (timing mode register)----Set the timer counter operating mode (not bit addressable

GATE C/T M1 M0 GATE C/T M1 M0

GATE: Controls T1. When it is 1, T1 will only be started when pin 3.3 is high and TR1 is set to 1.

C/T: When set to 1, T1 acts as a counter and 0 acts as a timer.

M1, M0:

When M1 = 0, M0 = 0, working mode 0

When M1 = 0 and M0 = 1, the working mode is 1. At this time, TH1 and TL1 form a 16-bit counter.

When M1 = 1, M0 = 0, working mode 2, 8-bit automatic reload timer

When M1 = 1, M0 = 1, working mode 3, T1 counting

SCON (Serial Port Control Register)

SM0 SM1 SM2 REN TB8 RB8 TI RI

SM2: Multi-machine communication 0 dual-machine 1 multi-machine

REN: Accept control 0 prohibited 1 allowed

TB8: The ninth digit of the sent data

TI: Transmit interrupt flag bit

SM0SM1: Working mode selection bit

0 0 shift register fosc/12

0 1 10-bit asynchronous reception and reception variable

1 0 11-bit asynchronous reception and transmission fosc/64 or fosc/32

1 1 11 variable