IIC Communication Principle

Overview:

I2C (IIC, Inter-Integrated Circuit), a two-wire serial bus, was developed by PHILIPS to connect microcontrollers and their peripherals.

It is a serial bus composed of data line SDA and clock SCL, which can send and receive data. It can transmit data bidirectionally between CPU and controlled IC, and between IC and IC. The high-speed IIC bus can generally reach more than 400kbps.

IIC is a half-duplex communication method.

Multi-master I2C bus system architecture

I2C Protocol:

Idle state

Start signal

Stop signal

Response signal

Data validity

data transmission

state:

1) Idle state

When the SDA and SCL signal lines of the I2C bus are both at high level, it is defined as the idle state of the bus. At this time, the output stage field effect transistors of each device are in the cut-off state, that is, the bus is released, and the level is pulled up by the pull-up resistors of the two signal lines.

2) Start signal and stop signal

Start signal: When SCL is high, SDA jumps from high to low; the start signal is a level jump timing signal, not a level signal.

Stop signal: When SCL is high, SDA jumps from low to high; the stop signal is also a level jump timing signal, not a level signal.

3) ACK signal

Each time the transmitter sends a byte, it releases the data line during clock pulse 9, and the receiver feeds back an acknowledgement signal. When the acknowledgement signal is at a low level, it is defined as a valid acknowledgement bit (ACK for short), indicating that the receiver has successfully received the byte; when the acknowledgement signal is at a high level, it is defined as a non-acknowledgement bit (NACK), generally indicating that the receiver has not successfully received the byte.

The requirement for feedback of the valid acknowledgement bit ACK is that the receiver pulls the SDA line low during the low level period before the 9th clock pulse, and ensures that it is a stable low level during the high level period of the clock. If the receiver is the master controller, it sends a NACK signal after it receives the last byte to notify the controlled transmitter to end the data transmission and release the SDA line so that the master receiver can send a stop signal P.

4) Data validity:

When the I2C bus is transmitting data, the data on the data line must remain stable while the clock signal is at a high level. The high or low level state of the data line is allowed to change only when the signal on the clock line is at a low level.

That is, the data must be ready before the rising edge of SCL arrives, and must be stable before the falling edge arrives.

5) Data transmission

Each bit of data transmitted on the I2C bus has a corresponding clock pulse (or synchronous control), that is, with the cooperation of the SCL serial clock, each bit of data is transmitted serially on SDA bit by bit. The transmission of data bits is edge triggered.

Analysis of IIC underlying driver: 24C02 operation

EEPROM(24C02):

The total capacity is 256 (2K/8) bytes.

Interface: IIC

24C02 byte write timing:

24C02 read timing: