ATmega16 Core Introduction

Figure 3. Block diagram of the AVR architecture

To achieve the highest performance and parallelism, AVR uses Harvard architecture with independent data and program buses. Instructions in the program memory are run through a one-stage pipeline. The CPU reads the next instruction while executing one instruction (called prefetch in this article). This concept enables single-clock cycle execution of instructions. The program memory is FLASH that can be programmed online. The 

fast access register file includes 32 8-bit general-purpose working registers with an access time of one clock cycle. This enables single-clock cycle ALU operation. In a typical ALU operation, two operands in the register file are accessed simultaneously, then the operation is performed, and the result is sent back to the register file. The entire process takes only one clock cycle. There are

6 registers in the register file that can be used as 3 16-bit indirect addressing register pointers to address the data space, achieving efficient address operations. One of the pointers can also be used as an address pointer for the program memory lookup table. These additional function registers are the 16-bit X, Y, and Z registers.

The ALU supports arithmetic and logical operations between registers and between registers and constants. The ALU can also perform single-register operations. After the operation is completed, the contents of the status register are updated to reflect the result of the operation.

Program flow is controlled by conditional/unconditional jump instructions and call instructions, which directly address the entire address space. Most instructions are 16 bits long, that is, each program memory address contains a 16-bit or 32-bit instruction. The

program memory space is divided into two areas: the boot area and the application area. Both areas have special lock bits to achieve read and read/write protection. The SPM instruction used to write to the application area must be located in the boot area. The

program counter (PC) of the return address during interrupts and subroutine calls is saved in the stack. The stack is located in the general data SRAM, so its depth is only limited by the size of the SRAM. In the reset routine, the user must first initialize the stack pointer SP. This pointer is located in the I/O space and can be read and written. The data SRAM can be accessed through 5 different addressing
modes .

The AVR memory space is a linear planar structure.

The AVR has a flexible interrupt module. The control register is located in the I/O space. The status register has a global interrupt enable bit. Each interrupt has an independent interrupt vector in the interrupt vector table. The priority of each interrupt is related to its position in the interrupt vector table. The lower the interrupt vector address, the higher the priority. The

I/O memory space contains 64 directly addressable addresses, which serve as control registers for CPU peripherals, SPI, and other I/O functions. Mapping to the data space is the address 0x20 - 0x5F after the register file.