Freescale MC9S08AW60 Assembly Learning Notes (VI)

Delay is a function that is often used in assembly. That is, the MCU does nothing but delays for a period of time. The MCU itself has timers and counters, which can be used to realize delay. However, a programmer naturally hopes that the function to be realized is easier to control. We use code and program to realize delay, that is, software delay. The specific method is: through A, H:X increase and decrease instructions, no operation instructions nop and brn and corresponding transfer instructions, and then use the loop structure to realize the delay function. Since it is a delay, it is best to know how long the delay is. What we know is that the MCU bus clock frequency is 4MHz, so a bus cycle takes 0.25us. In this way, as long as we know the bus cycle occupied by each instruction, we can calculate how long our program runs. The same is true for delay. Of course, these require mathematical knowledge. Don't worry, calculus is not needed. As long as you are patient, it is not difficult to accurately calculate the delay time.

Example: Design a delay subroutine with a delay of 10ms, given that the MCU bus clock frequency is 4MHz.

Analysis: Since the bus clock frequency is 4MHz, a bus cycle takes 0.25us, and a 10ms delay requires the execution of instructions equivalent to 40,000 bus cycles. We can first design a subroutine Re_cycle to achieve a smaller delay, and then call the subroutine multiple times to achieve a longer delay. The code is as follows:

 org $0070
num ds.b 1
count1 ds.b 1

 org $1860
re_cycle: ;4+7*70+6=500T=125us
　　mov #70T,num ;4T
　　dbnz num,* ;7T
　　rts ;6T
delay_10ms: ;[4+78*(5+7+500)]+4+7*7+6=39999T
　　mov #78T,count1 ;4T
re_call:
　　bsr re_cycle ;5T
　　dbnz count1,re_call ;7T
　　mov #07T,count1 ;4T
　　dbnz count1,* ;7T
　　rts ;6T

main:
　　bsr delay_10ms ;5~6T
again:
　　nop
　　jmp again


 org $fffe
 dc.w main

The time taken by each instruction has been marked. What is needed is delicate design and precise calculation. For example, the design of the Re_cycle subroutine takes exactly 500T for three instructions. Here we need to explain the DBNZ instruction. The function it implements is to compare the number in the previous variable with 0 by decrementing it by 1. If they are not equal, it will transfer to the following address and execute it. If they are equal, it will end the instruction (that is, if the decrement is not 0, the instruction will be transferred). Here we must ask what * represents. It represents the address of the instruction where it is located. The dbnz num,* instruction can be interpreted as num decrementing by 1 and not equal to 0, then it will come back and execute the statement again, and it will end when num decremented by 1 is equal to 0. From the comments, it can be seen that the total time taken by the delay_10ms subroutine to complete is 39999T, plus the call to the delay_10ms subroutine in the main program takes 5~6T. In this way, if delay_10ms is not called once, a delay of about 10ms for 40004~40005 bus cycles can be achieved. Of course, if the design is good enough, it can be even more precise, the closer to 40,000 T the better.

The above implements a delay of 10ms. What if we want to implement 100ms, 500ms, 1ms, and 0.1ms? The same method relies on sophisticated design and precise calculation. The following are subroutines for delays of 1ms and 500ms:

 org $0070
num ds.b 1
count1 ds.b 1
count2 ds.b 1

 org $1860
re_cycle: ;4+7*70+6=500T=125us
　　mov #70T,num
　　dbnz num,*
　　rts

delay_1ms: ;[4+(5+7+500)*8+6]=4106T
　　mov #08t,count
　　re_call:
　　bsr re_cycle                
　　dbnz count,re_call
　　rts

delay_10ms: ;39999T
　　mov #78T,count1
re_call:
　　bsr re_cycle
　　dbnz count1,re_call
　　mov #07T,count1
　　dbnz count1,*
　　rts

delay_500ms: ;The idea is to repeat delay_10ms 50 times, so there will definitely be some inaccuracies, please forgive me.
　　mov #50T,count2
re:
　　bsr delay_10ms
　　dbnz count2,re
　　rts

main:

　　bsr delay_1ms
　　bsr delay_10ms

　　bsr delay_500ms
again:
　　nop
　　jmp again


 org $fffe
 dc.w main