ARM bare metal CLOCK

1. What is a clock? Why does SoC need a clock?

(1) In real life, clocks are used to record time, while in SOC, clocks represent a synchronized beat.

(2) The various components in the SOC work together under the influence of the clock system.

2. How to obtain the clock?

(1) External input clock signal: SOC inputs clock signal from the outside through the pin.

(2) External crystal oscillator + internal clock generator generates clock signal.

(3) External crystal oscillator + internal clock generator + internal PLL generates high-frequency clock + internal divider (each component has its own divider) generates various frequency clocks.

3. Clock setting steps:

(1) PLL is not used yet.

(2) Set the lock time and use the default value.

(3) Set the target value after PLL frequency multiplication.

(4) Set the frequency division

(5) Set the MUX of various PLLs and use PLL.

4. Assembly code implementation

#define ELFIN_CLOCK_POWER_BASE0xE0100000

#define APLL_LOCK_OFFSET0x00

#define MPLL_LOCK_OFFSET0x08

#define APLL_CON0_OFFSET0x100

#define APLL_CON1_OFFSET0x104

#define MPLL_CON_OFFSET0x108

#define CLK_SRC0_OFFSET0x200

#define CLK_SRC1_OFFSET0x204

#define CLK_SRC2_OFFSET0x208

#define CLK_SRC3_OFFSET0x20c

#define CLK_SRC4_OFFSET0x210

#define CLK_SRC5_OFFSET0x214

#define CLK_SRC6_OFFSET0x218

#define CLK_SRC_MASK0_OFFSET 0x280

#define CLK_SRC_MASK1_OFFSET 0x284

#define CLK_DIV0_OFFSET0x300

#define CLK_DIV1_OFFSET0x304

#define CLK_DIV2_OFFSET0x308

#define CLK_DIV3_OFFSET0x30c

#define CLK_DIV4_OFFSET0x310

#define CLK_DIV5_OFFSET0x314

#define CLK_DIV6_OFFSET0x318

#define CLK_DIV7_OFFSET0x31c

#define APLL_MDIV 0x7d // 125

#define APLL_PDIV 0x3

#define APLL_SDIV 0x1

#define MPLL_MDIV0x29b // 667

#define MPLL_PDIV0xc

#define MPLL_SDIV0x1

#define set_pll(mdiv, pdiv, sdiv)(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)

#define APLL_VALset_pll(APLL_MDIV,APLL_PDIV,APLL_SDIV)

#define MPLL_VALset_pll(MPLL_MDIV,MPLL_PDIV,MPLL_SDIV)

.global clock_init

clock_init:

ldrr0, =ELFIN_CLOCK_POWER_BASE

// Set CLK_SRC0 register bit[0] to select FINPLL

ldrr1, =0x0

strr1, [r0, #CLK_SRC0_OFFSET]

// After setting the PLL, it takes a certain amount of time for the clock to rise from the input source FIN to the target frequency.

ldrr1,=0x00000FFF

strr1,[r0, #APLL_LOCK_OFFSET]

str r1, [r0, #MPLL_LOCK_OFFSET]

// Set APLL_CON0 register, FOUT = MDIV*FIN/(PDIV*2^(SDIV-1))=0x7d*24/(0x3*2^(1-1))=1000 MHz

ldrr1, =APLL_VAL

strr1, [r0, #APLL_CON0_OFFSET]

// Set MPLL_CON0 register, FOUT = MDIV*FIN/(PDIV*2^SDIV)=0x29b*24/(0xc*2^1)= 667 MHz

ldrr1, =MPLL_VAL

strr1, [r0, #MPLL_CON_OFFSET]

// Set the CLK_DIV0 register to clear bits [0~31].

ldr r1, [r0, #CLK_DIV0_OFFSET]

ldrr2, =0xFFFFFFFF

bicr1, r1, r2

// Set the CLK_DIV0 register [0~31] to write related bits.

ldrr2, =((0<<0) | (4<<4) | (4<<8) | (1<<12) | (3<<16) | (1<<20) | (4<<24) | (1<<28))

orrr1, r1, r2

strr1, [r0, #CLK_DIV0_OFFSET]

// Set up the CLK_SRC0 register.

ldrr1, [r0, #CLK_SRC0_OFFSET]

ldrr2, =((1<<0) | (1<<4) | (1<<8) | (1<<12) | (0<<16) | (0<<20) | (0<<24) | (1<<28))

orrr1, r1, r2

strr1, [r0, #CLK_SRC0_OFFSET]

movpc, lr

Reference: "ARM Bare Metal Complete Works---Teacher Zhu Youpeng"