Common ARM concepts that you must know!

Introduction: This article lists 22 common concepts about ARM, including some usage precautions, ARM startup code design, ARM processor operation mode, exception types supported by ARM architecture and some basic operation methods, etc.

1. Explanation of some common English abbreviations in ARM

MSB: Most Significant Bit;

LSB: least significant bit;

AHB: Advanced High-Performance Bus;

VPB: VLSI peripheral bus that connects on-chip and off-chip functions;

EMC: External Memory Controller;

MAM: Memory Acceleration Module;

VIC: Vectored Interrupt Controller;

SPI: full-duplex serial interface;

CAN: Controller Area Network, a serial communication protocol;

PWM: Pulse Width Modulator;

ETM: Embedded Trace Macro;

CPSR: Current Program Status Register;

SPSR: Program Protection Status Register;

2. Notes on using MAM:

A: When changing the MAM timing value, you must first turn off the MAM by writing 0 to MAMCR, then write the new value to MAMTIM. Finally, write the corresponding value of the required operating mode to MAMCR and turn the MAM on again.

For system clocks below 20MHz, MAMTIM is set to 001. For system clocks between 20MHz and 40MHz, it is recommended to set the Flash access time to 2cclk, and for system clocks above 40MHz, it is recommended to use 3cclk.

3. Precautions for using VIC

A: If the code is running in on-chip RAM and the application needs to call interrupts, the interrupt vector must be remapped to Flash address 0x0. This is done because all exception vectors are located at address 0x0 and above. This is achieved by configuring register MEMMAP (located in the system control block) to user RAM mode. The user code is linked so that the interrupt vector table is loaded at 0x4000 0000.

4. Arm startup code design

Answer: The ARM startup code directly programs the processor core and hardware controller, generally using assembly language. The startup code generally includes:

Interrupt vector table

Initialize the memory system

Initialize the stack and initialize ports and devices with special requirements

Initialize the user program execution environment

Changing the processor mode

Calling the main application

5. Difference between IRQ and FIQ

A: IRQ and FIQ are two programming modes of ARM processors. IRQ means interrupt mode and FIR means fast interrupt mode. For FIQ you must do your business and leave this mode as soon as possible. IRQ can be interrupted by FIQ, but IRQ cannot interrupt FIQ. In order to make FIQ faster, this mode has more shadow registers. FIQ cannot call SWI (software interrupt). FIQ must also disable interrupts. If a FIQ routine must re-enable interrupts, it is too slow and should be IRQ instead of FIQ.

6. ARM processor's response process to abnormal interrupt

Answer: The arm processor's response to abnormal interrupts is as follows:

Save the current state of the processor, interrupt mask bit and each condition flag bit;

Set the corresponding bit in the current program status register CPSR;

Set register lr_mode to the return address;

Set the program counter value PC to the interrupt vector address of the exception interrupt and jump to the corresponding exception interrupt to execute.

7. The difference between arm instructions and Thumb instructions

Answer: In the ARM architecture, the instructions in the ARM instruction set are 32-bit instructions, and their execution efficiency is very high. For application systems with a 16-bit storage system data bus, the ARM system provides the Thumb instruction set. The Thumb instruction set is a subset of the ARM instruction set that is re-encoded, and the instruction length is 16 bits. Usually when the processor executes an ARM program, the processor is said to be in ARM state; when the processor executes a Thumb program, the processor is said to be in Thumb state. The Thumb instruction set does not change the programming model of the ARM system layer, but only adds some restrictions to the model. The operands of the data processing instructions in the Thumb instruction set are still 32 bits, and the instruction addressing address is also 32 bits.

8. What is ATPCS

Answer: In order to enable separately compiled C language programs and assembly programs to call each other, certain rules must be specified for calling subroutines. ATPCS is the basic rules for calling subroutines in ARM programs and Thumb programs. These rules include register usage rules, data stack usage rules, parameter passing rules, etc.

9. Mixed use of arm programs and Thumb programs

A: Generally, Thumb programs are more compact than ARM programs, and for systems with 8-bit or 16-bit memory, using Thumb programs is more efficient. However, in some cases, the program must run in ARM state, and then it is necessary to mix ARM and Thumb programs.

When speed is important, arm programs should be used;

Some functions can only be completed by the arm program. For example: use or disable abnormal interrupts;

When the processor enters the exception interrupt handler, the program state switches to the ARM state, that is, some instructions at the entrance of the exception interrupt handler are ARM instructions, and then the program can switch to the Thumb state as needed. Before the exception interrupt program returns, the program switches to the arm state again.

ARM processors always start execution from ARM state. Therefore, if you want to run a Thumb program in a debugger, you must add an arm program header to the Thumb program, then switch to Thumb state and execute the Thumb program.

10.ARM processor operating mode

Answer: ARM microprocessor supports 7 operating modes, namely:

User mode (usr): the normal program execution state of the arm processor;

Fast interrupt mode (fiq): used for high-speed data transmission or channel management;

External interrupt mode (irq): used for general interrupt processing;

Management mode (svc): protection mode used by the operating system;

Data access termination mode (abt): This mode is entered when data or instruction prefetching is terminated, and is used for virtual storage and storage protection;

System mode (sys): runs privileged operating system tasks;

Undefined instruction abort mode (und): This mode is entered when an undefined instruction is executed and can be used to support software emulation of hardware coprocessors.

11. Exception types supported by the arm architecture

A: The exceptions and their specific meanings supported by the ARM architecture are as follows (the numbers in the circle indicate the priority):

Reset ①: When the reset level of the processor is valid, a reset exception occurs, and the program jumps to the reset exception location for execution (exception vector: 0x0000, 0000);

Undefined instruction⑥: When the ARM processor or coprocessor encounters an instruction that cannot be processed, an undefined exception is generated. This exception mechanism can be used for software simulation (exception vector: 0x0000, 0004);

Software interrupt ⑥: SWI instruction is executed, which can be used to call privileged operation instructions in user mode. This exception mechanism can be used to implement system function calls (exception vector: 0x0000, 0008);

Instruction prefetch abort⑤: If the address of the processor's prefetch instruction does not exist, or the address does not allow the current instruction to access, the memory will send an abort signal to the processor. When the prefetch instruction is executed, an instruction prefetch abort exception will be generated (exception vector: 0x0000, 000C);

Data abort②: If the address of the instruction for data access by the processor does not exist, or the address does not allow the current instruction to access, a data abort exception is generated (exception vector: 0x0000, 0010);

IRQ④ (External Interrupt Request): When the processor's external interrupt request pin is valid and the I bit in the CPSR is 0, an IRQ exception is generated. The system's peripherals can use this exception to request interrupt service (exception vector: 0x0000, 0018);

FIQ③ (fast interrupt request): When the processor's fast interrupt request pin is valid and the F bit in the CPSR is 0, a FIQ exception is generated (exception vector: 0x0000, 001C).

Note: The exception vectors 0x0000, 0014 are reserved exception vectors.

12.Memory format of arm architecture

Answer: There are two memory formats for the ARM architecture:

Big-endian format: The high byte of word data is stored in the low address, and the low byte of word data is stored in the high address;

Little-endian format: Contrary to the big-endian storage format, the high address stores the high byte of the data and the low address stores the low byte of the data.

13.ARM register summary:

ARM has 16 32-bit registers (r0 to r15).

r15 acts as the program register PC, r14 (link register) stores the return address of the subroutine, and r13 stores the stack address.

ARM has a current program status register: CPSR.

Some registers (r13, r14) will generate new instances when an exception occurs, such as IRQ processor mode, when the processor uses r13_irq and r14_irq

ARM's subroutine calls are very fast because the subroutine's return address does not need to be stored in the stack.

14. Reasons for memory remapping (Remap):

The FIQ handler in the Flash memory does not need to consider the memory boundary problem caused by remapping; the use of SRAM and Boot Block vectors used to handle segment boundary arbitration in the code space is greatly reduced;

Provides space to store constants for jumps that exceed the range of single-word transfer instructions.

Remapping in ARM refers to the mapping of reallocating the memory address space by writing a certain function register bit operation during the program execution. A typical application is that the application is stored in Flash/ROM. Initially, these memory addresses start from 0, but the read time of these memories is longer than SRAM/DRAM, resulting in a low internal execution frequency. Therefore, the code is generally moved to SRAM/DRAM in the previous section of the program, and then the memory space is remapped, and the corresponding SRAM/DRAM is mapped to address 0. Re-executing the program can achieve the purpose of high-speed operation.