RISC-V Popular Science: Understanding the Open Source ISA Architecture

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Understanding RISC and CISC

RISC is a computer architecture philosophy proposed in the 1980s as an alternative to the commercial architectures offered at the time by Intel, Motorola, and just about everyone else. Originally called "complex instruction set computers," or CISC, this architecture relied on dense instruction sets to implement the kinds of operations deemed useful and necessary. However, a number of research teams, including IBM and UC Berkeley, found that compilers often ended up using a small subset of these complex instruction sets. This and other findings called into question the need for larger instruction sets, placing a focus on simplicity as a means of increasing efficiency.

In general, RISC is the opposite of CISC in many ways. Typically, a CISC central processing unit (CPU) has a few registers and a large set of instructions, most of which can access memory, while a RISC CPU has many registers and a very limited instruction set, with memory access limited to a few load and store instructions.

To illustrate the difference between complex and simple instructions, Table 1 shows a comparison of code for incrementing a counter variable using a CISC CPU (NXP's S08) and a RISC CPU (ARM Cortex M0+).

In this table, CISC allows incrementing variables in a single instruction, while RISC requires accessing memory via loads and stores. Although this shows the difference in code size, it is not an apples to apples comparison as there are many differences between the architectures, so this does not prove that one is technically superior to the other.

Today, Intel's x86/x64 architecture proves that CISC microprocessors have not been replaced by RISC, while the ARM architecture proves that RISC has dominated the mobile device market.

RISC-V History

The acronym RISC was coined around 1980 by Professor David Patterson of UC Berkeley, who collaborated with Professor John Hennessy of Stanford University to produce their famous books Computer Organization and Design and Computer Architecture: A Quantitative Approach. For their work on RISC architecture, they received the ACM AM Turing Award in 2017.

Fast forward from 1980 to 2010, and development of the fifth generation RISC research project began, which would eventually be known as RISC-V.

RISC-V International - an open ISA

RISC-V is an open instruction set architecture (ISA), which means that you can freely implement a RISC-V CPU in a microprocessor or microcontroller without having to pay royalties to anyone who uses this ISA.

RISC-V International is a global non-profit organization that owns and maintains the RISC-V ISA intellectual property. One of its main goals is to keep the design of RISC-V based on simplicity and performance, rather than focusing on commercial interests. For this reason, RISC-V International relies on its members who represent the microprocessor ecosystem community, from individuals to organizations such as Google, Intel and Nvidia. Becoming a member has many benefits, including the possibility to contribute to the design of the ISA, as well as voting to approve proposed changes. In Figure 1 below, you can see a high-level timeline of the development of RISC-V over the years.

RISC-V ISA and extension conventions

As a fifth-generation research project that began in 1980, RISC-V is an experienced architecture designed to succeed where others may have failed in the past, and RISC-V is designed to learn from any potential past mistakes.

For this reason, RISC-V is designed as a modular ISA, rather than a traditional incremental ISA. This means that a RISC-V implementation consists of a mandatory base ISA and a number of ISA extensions so that a custom CPU can be tailored to the needs of an application.

The naming convention for custom ISAs consists of the letters RV (for RISC-V) followed by the bit width and variant identifier.

For example, the RV32IMAC shown in Figure 2 represents:

RV32I: 32-bit CPU with basic integer ISA

M: Integer multiplication and division extension

A: Atomic instruction extension

C: Compressed Instruction Extensions

The compiler is informed of the extensions included in the target CPU so that it generates the best possible code. If the code contains instructions for which an extension is missing, the hardware traps and executes the software functions from the standard library.

Basic integer ISA

With only 47 instructions, the RV32I base integer ISA implements the operations absolutely necessary to implement basic functionality for 32-bit integers (its 64-bit variant is RV64I). This ISA is encoded in 32 bits and includes the following instructions:

Add to

Subtraction

Bitwise Operations

Loading and storing

jump

Branch Offices

The base ISA also specifies 32 CPU registers, all 32 bits wide, plus the program counter. The only special register is x0, which always reads 0, as implemented in many previous RISC ISAs.

Although all registers shown in Table 2 are available for general use, the Application Binary Interface (ABI) specifies the purpose of each register according to its calling convention. This means that some registers should hold temporary or saved data, pointers, return addresses, and so on.

RISC-V multiplication and floating point

The RV32M extension implements 8 instructions to perform multiplication and division on integers (RV64M adds 5 instructions to these 8 instructions).

The RV32F extension adds 32 independent registers for 32-bit floating point numbers and 26 floating point instructions. Similarly, the RV32D extension uses 32 64-bit floating point registers to support double-precision 64-bit floating point numbers.

RISC-V compressed instructions

The RV32C extension is a neat addition to the RISC-V ISA, as it provides an alternative 16-bit encoding for a special subset of existing instructions.

After analyzing countless lines of code generated by modern optimizing compilers, the creators of RISC-V identified the most popular instructions and created 16-bit versions that gave up some of their functionality for the full 32-bit version, which is in the RV32I base ISA anyway.

This compression is possible due to the following instructions:

1. Some registers are more popular than others.

2. One operand is usually overwritten.

3. There are some preferred immediate values.

This allows encoding instructions with a limited number of registers as operands, specifying only 2 registers instead of 3, using small immediate values, all in 16 bits.

By compressing the most frequently used instructions, you have a better chance of significantly compressing your program.

Other RISC-V extensions

There are many additional extensions that implement all the features expected from a modern microprocessor. This includes extensions to the embedded base ISA (RV32E), atomic operations (A), bitwise operations (B), vector operations (V), and more.

RISC-V Implementation

Many companies make various RISC-V cores in their microcontrollers, microprocessors, and SoCs. One example is SiFive, the first company to make chips based on the RISC-V ISA. Their chips range from low-end microcontrollers all the way up to high-performance SoCs.

However, actual RISC-V projects are not limited to integrated circuits. There are a large number of ongoing projects in many areas such as compilers, simulators, development environments, operating systems, etc.

bobde163

I learned a lot, thanks for sharing

freebsder

Thanks for the science.