Detailed explanation of MCS-51 single chip microcomputer instructions

There are 18 instructions in the MCS-51 series of microcontrollers that begin with A, namely:

ACALL addr11 ADD A，Rn ADD A，direct ADD A，@Ri ADD A，#data ADDC A，RnADDC A，direct ADDC A，@Ri ADDC A，#data AJMP addr11 ANL A，Rn ANL A，direct ANL A，@Ri ANL A，#data ANL direct，A ANL direct，#data ANL C，bit ANL C，/bit

1、ACALL addr11

Instruction name: Absolute call instruction

Instruction code: A10 A9 A8 10001 A7 A6 A5 A4 A3 A2 A1 A0

Instruction function: construct the destination address and call the subroutine. The method is to use the 11-bit address (al0~a0) provided by the instruction.

Replace the lower 11 bits of PC, and the upper 5 bits of PC remain unchanged.

Operation content:

PC←(PC)+2

SP←(SP)+1

(SP)←(PC)7～0

SP←(SP)+1

(SP)←(PC)15～8

PC10～0←addrl0～0

Number of bytes: 2

Machine cycles: 2

Instructions for use: Since the instruction only gives the lower 11 bits of the subroutine entry address, the calling range is 2KB.

2、ADD A，Rn

Instruction name: Register addition instruction

Instruction code: 28H～2FH

Instruction function: Add the contents of the accumulator to the contents of the register

Operation content: A←(A)+(Rn), n＝0～7

Number of bytes: 1

Machine cycle; 1

Affected flags: C, AC, OV

3、ADD A，direct

Instruction name: Direct addressing addition instruction

Instruction code: 25H

Instruction function: Add the accumulator contents to the internal RAM unit or the dedicated register contents

Operation content: A←(A)+(direct)

Number of bytes: 2

Machine cycles: 1

Affected flags: C, AC, OV

4、ADD A，＠Ri ’

Instruction name: Indirect addressing addition instruction

Instruction code: 26H～27H

Instruction function: Add the contents of the accumulator to the contents of the lower 128 units of the internal RAM

Operation content: A←(A)+((Ri)), i＝0,1

Number of bytes: 1

Machine cycles: 1

Affected flags: C, AC, OV

5、ADD A，#data

Instruction name: Immediate addition instruction

Instruction code: 24H

Instruction function: add the accumulator contents to the immediate value

Operation content: A←(A)+data

Number of bytes: 2

Machine cycles: 1

Affected flags: C, AC, OV

6、ADDC A、Rn

Instruction name: Register carry addition instruction

Instruction code: 38H～3FH

Instruction function: Add the accumulator contents, register contents, and carry bit

Operation content: A←(A)+(Rn)+(C), n＝0～7

Number of bytes: 1

Machine cycles: 1

Affected flags: C, AC, OV

7、ADDC A、direct

Instruction name: Direct addressing with carry addition instruction

Instruction code: 35H

Instruction function: Add the accumulator contents, the lower 128 cells of the internal RAM or the special register contents and the carry bit.

Operation content: A←(A)+(direct)+(C)

Number of bytes: 2

Machine cycles: 1

Affected flags: C, AC, OV

8、ADDC A，＠Ri

Instruction name: Indirect addressing with carry addition instruction

Instruction code: 36H～37H

Instruction function: Add the accumulator contents, the lower 128 units of the internal RAM, and the carry bit

Operation content: A←(A)+((Ri))+(C), i＝0,1

Number of bytes: 1

Machine cycles: 1

Affected flags: C, AC, OV

9、ADDC A、#data

Instruction name: Immediate number with carry addition instruction

Instruction code: 34H

Instruction function: Add the accumulator contents, immediate data and carry bit

Operation content: A←(A)+data+(C)

Number of bytes: 2

Machine cycles: 1

Affected flags: C, AC, OV

10、AJMP addr11

Instruction name: Absolute transfer instruction

Instruction code: A10 A9 A8 1 0 0 0 1 A7 A6 A5 A4 A3 A2 A1 A0

Instruction function: construct the destination address and realize program transfer. The method is to replace the lower 11 bits of PC with the 11-bit address provided by the instruction, while the upper 5 bits of PC remain unchanged.

Operation content: PC←(PC)+2

PCl0～0←addrll

Number of bytes: 2

Machine cycles: 2

Instructions for use: Since the minimum value of addrll is 000H and the maximum value is 7FFH, the address transfer range is 2KB.

11、ANL A，Rn

Instruction name: Register logical and instruction

Instruction code: 58H～5FH

Instruction function: Logic of accumulator contents and register contents

Operation content: A←(A)∧(Rn), n＝0～7

Number of bytes: 1

Machine cycles: 1

12、ANL A，direct

Instruction name: Direct addressing logical and instruction

Instruction code: 55H

Instruction function: Logic addition of accumulator contents and lower 128 units of internal RAM or special register contents

Operation content: A←(A)∧(diret)

Number of bytes: 2

Machine cycles: 1

13、ANL A，＠Ri

Instruction name: Indirect addressing logic and instruction

Instruction code: 56H～57H

Instruction function: Logic addition of accumulator contents and internal RAM lower 128 units contents

Operation content: A←(A)∧((Ri)) i＝0，1

Number of bytes: 1

Machine cycles: 1

14、ANL A，#data

Instruction name: Immediate logical AND instruction

Instruction code: 54H

Instruction function: Logic and immediate value of accumulator contents

Operation content: A←(A)∧data

Number of bytes: 2

Machine cycles: 1

15、ANL direct，A

Instruction name: Accumulator logical and instruction

Instruction code: 52H

Instruction function: logical and accumulator contents of the lower 128 units of the internal RAM or the dedicated register contents

Operation content: direct←(A)∧(direct)

Number of bytes: 2

Machine cycles: 1

16、ANL direct， #data

Instruction name: Logical and instruction

Instruction code: 53H

Instruction function: internal RAM lower 128 units or special register contents logical and immediate data

Operation content: direct←(direct)∧data

Number of bytes: 3

Machine cycles: 2

17、ANL C，bit

Instruction name: Bit logic and instruction

Instruction code: 82H

Instruction function: carry flag logic and direct addressing bit

Operation content: C←(C)∧(bit)

Number of bytes: 2

Machine cycles: 2

18、ANL C，／bit

Instruction name: Bit logic and instruction

Instruction code: B0H

Instruction function: Carry flag logic and direct addressing bit inverse

Operation content: C←(C)∧(bit)

Number of bytes: 2

Machine cycles: 2

There are 10 instructions in the MCS-51 series of microcontrollers that begin with C, namely:

CJNE A，dircet，rel CJNE A，#data，rel CJNE Rn，#data，rel CJNE ＠Ri，#data，rel CLR A CLR C CLR bit CPL A CPL C CPL bit

1、CJNE A，dircet，rel

Instruction name: Numerical comparison transfer instruction

Instruction code: B5H

Instruction function: Compare the accumulator contents with the lower 128 bytes of the internal RAM or the dedicated register contents, and transfer if they are not equal.

Operation content: If (A) = (direct), then PC←(PC)+3, C←0

If (A)＞(direct), then PC←(PC)+3+rel, C←0

If (A) < (direct), then PC ← (PC) + 3 + rel, C ← 1

Number of bytes: 3

Machine cycles: 2

2、CJNE A，#data，rel

Instruction name: Numerical comparison transfer instruction

Instruction code: B4H

Instruction function: Compare the accumulator content with the immediate value, and jump if they are not equal.

Operation content: If (A) = data, then PC←(PC)+3, C←0

If (A)＞data, then PC←(PC)+3+rel, C←0

If (A) < data, then PC ← (PC) + 3 + rel, C ← 1

Number of bytes: 3

Machine cycles: 2

3、CJNE Rn，#data，rel

Instruction name: Numerical comparison transfer instruction

Instruction code: B8H～BFH

Instruction function: Compare the register content with the immediate value, and transfer if they are not equal.

Operation content: If (Rn) = data, then PC←(PC)+3, C←0

If (Rn)＞data, then PC←(PC)+3+rel, C←0

If (Rn)＜data, then PC←(PC)+3+rel, C←1

Number of bytes: 3

Machine cycles: 2

4、CJNE ＠Ri，#data，rel

Instruction name: Numerical comparison transfer instruction

Instruction code: B6H～B7H

Instruction function: Compare the contents of the lower 128 units of the internal RAM with the immediate value, and transfer if they are not equal.

Operation content: If ((Ri))=data, then PC←(PC)+3, C←0

If ((Ri))＞data, then PC←(PC)+3+rel, C←0

If ((Ri))＜data, then PC←(PC)+3+rel, C←1

Number of bytes: 3

Machine cycles: 2

5、CLR A

Instruction name: Accumulator clear instruction

Instruction code: E4H

Instruction function: clear the accumulator to 0

Operation content: A←0

Number of bytes: 1

Machine cycles: 1

6、CLR C

Instruction name: Carry flag clear instruction

Instruction code: C3H

Instruction function: Carry bit cleared to 0

Operation content: C←0

Number of bytes: 1

Machine cycles: 1

7、CLR bit

Instruction name: Direct addressing bit clear 0 instruction

Instruction code: C2H

Instruction function: Direct addressing bit cleared to 0

Operation content: bit←0

Number of bytes: 2

Machine cycles: 1

8、CPL A

Instruction name: Accumulator negation instruction

Instruction code: F4H

Instruction function: invert the accumulator

Operation content: A←(A)

Number of bytes: 1

Machine cycles: 1

9、CPL C

Instruction name: Carry flag inversion instruction

Instruction code: B3H

Instruction function: Carry flag status inversion

Operation content: C←(c is negated)

Number of bytes: 1

Machine cycles: 1

10、 CPL bit

Instruction name: Direct addressing bit inversion instruction

Instruction code: B2H

Instruction function: Direct addressing bit inversion

Operation content: bit←(bit inversion)

Number of bytes: 2

Machine cycles: 1

There are 8 instructions in the MCS-51 series of microcontrollers that begin with D, namely:

DA A DEC A DEC Rn DEC direct DEC ＠Ri DIV AB DJNZ Rn，rel DJNZ direct，rel

1、DA A

Command name: Decimal adjustment command

Instruction code: D4H

Instruction function: Conditionally modify the result of BCD code addition operation

Operation content: If (A)3~0＞9∨(AC)＝1, then A3~0←(A)3~0+6

If (A)7～4＞9∨(C)＝1, then A7～4←(A)7～4+6

Young (A) 7～4＝9 ∧ (A) 3～0＞9, Law A 7～4 ← (A) 7～4+6

Number of bytes: 1

Machine cycles: 1

Instructions: DA instruction does not affect the overflow flag

2、DEC A

Instruction name: Accumulator minus 1 instruction

Instruction code: 14H

Instruction function: subtract 1 from the accumulator content

Operation content: A←(A)-1

Number of bytes: 1

Machine cycles: 1

3、DEC Rn

Instruction name: Register minus 1 instruction

Instruction code: 18H～1FH

Instruction function: register content minus 1

Operation content: Rn←(Rn)-1, n=0～7

Number of bytes: 1

Machine cycles: 1

4、DEC direct

Instruction name: Direct addressing minus 1 instruction

Instruction code: 15H

Instruction function: internal RAM lower 128 units and special register contents minus 1

Operation content: direct←(direct)-1

Number of bytes: 2

Machine cycles: 1

5、DEC ＠Ri

Instruction name: Indirect addressing minus 1 instruction