Problems and solutions in using external interrupts of single chip microcomputers

In the process of long-term use of 51 single-chip microcomputers, we found that when the single-chip microcomputer works in an environment with strong interference such as industrial production sites, sometimes an external interrupt defined as a falling edge trigger mode is generated. However, when the instrument is used to measure the INTX pin that has been sent to the single-chip microcomputer, the single-chip microcomputer cannot respond to the interrupt normally. After excluding the problems that may be caused by the program, the current state of the CPU is checked again, and it is found that the interrupt level, interrupt enable, and interrupt trigger mode also indicate that the interrupt should be responded to. After analysis and testing, it is found that the internal port latch of the single-chip microcomputer INTX pin is set to zero. When the port is blocked to zero, the interrupt request represented by the falling edge introduced from the pin will be lost, and the interrupt will certainly not be responded to. Since the program does not use instructions that can set the port latch to zero, and the generation of this situation has a certain randomness and does not occur frequently, it is believed that this phenomenon may be caused by the latch malfunction caused by circuit interference or noise. At the same time, we also believe that this malfunction is related to the internal structure and operation mode of the P3 port.

The P3 port of the external interrupt input terminal of the single-chip microcomputer is a quasi-bidirectional port with the second variation function. The internal structure of each bit is shown in Figure 1. When the variation function output is high, the bit port is a normal I/O port. At this time, if the I/O port is written, the data is written into the latch from the internal bus, and sent out of the pin after being inverted twice by the NAND gate and the MOS tube; if the I/O port is read, the latch must be set to 1 first to cut off the MOS tube, and the pin is pulled up to a high level by the internal load MOS tube (marked as a pull-up resistor in the figure), and then the input operation can be performed. When the input is low, it can be pulled to a low level, and the pin information enters the internal bus through two buffers; if the second function (variation function) is used, the input latch must also be set to 1 first. At this time, the pin is controlled by the variation function output. If the variation function input is required, the latch and variation output must be set to 1 at the same time to cut off the MOS tube, and the variation function input changes with the change of the pin. It is estimated that the P3.2 and P3.3 ports, which can only be used for input interrupts in the second function, may not have variable function output lines inside. Even if they do, they can only be pulled up to a fixed high level. It can be seen that the latch of the microcontroller P3 port must be set to 1 first, whether it is a general I/O port or a variable function input. After the microcontroller is reset, the status of all I/O ports is 1. Generally, the interrupt priority is defined in the system initialization program, and the microcontroller can respond to the interrupt after the interrupt is turned on. If the corresponding interrupt enable bit is turned off (set to 0), the interrupt valid signal (low level or falling edge) that needs to enter the microcontroller from the pin can still enter and set IE0 (or IE1) to 1, but it cannot cause an interrupt. Of course, the program can check IE to understand whether the interrupt source has generated an interrupt request.

The author noticed that there are two types of instructions for the microcontroller I/O port that implicitly involve writing to the I/O port latch.

The first type is the read I/O pin instruction. After executing the read I/O pin instruction, the state of the I/O port latch will become the same as the pin. If this instruction happens to be executed while the interrupt pin is at a low level, the latch will become 0 and the interrupt will no longer be able to enter.

The second category is read-modify-write latch instructions, such as SETBPX.Y and JBCPX.Y, LABEL, etc. When these instructions are executed, they always read all 8 bits of data from the I/O port first, make certain modifications or judgments, and then write them back to the latch.

The first type of instructions are not used in the author's program, but the second type of instructions are used. However, they do not operate on P3.2 (or P3.3), but on P3.4 and P3.5 (because P3.4 and P3.5 are used as ordinary I/O ports in the system). However, we believe that it is possible that when executing this type of instruction to modify the latch bits of P3.4 and P3.5, P3.2 (or P3.3) is mistakenly written as 0 due to strong interference, resulting in the above situation. In order to verify this, we removed the instructions that operate on P3.4 and P3.5 in the program and found that the phenomenon of interrupt failure basically disappeared. However, in very rare cases, interrupt failure still occurred. This very rare phenomenon is purely caused by random interference.

In order to completely solve the problem of interruption inaccessibility, the following two measures are adopted:

(1) Abandon the remaining ports of P3 and do not use them as ordinary I/O ports, but replace them with external expansion interfaces of the microcontroller;

(2) Before the interrupt service routine is about to exit, write 1 to the P3.2 (or P3.3) port so that the latch state of the P3.2 (or P3.3) bit is 1 before the next interrupt arrives, thereby ensuring that no interrupt request is missed.

After making the above two improvements to the system, the interrupt loss phenomenon has never occurred again.

references

1. Sun Yucai. MCS-51 series single-chip microcomputers and their applications. Nanjing: Southeast University Press, 1987