Design of Embedded Minimum System Based on MC9328MX1

2 pieces of K4S281632, one piece is high 16 bits, the other is low 16 bits. The 2 pieces of K4S281632 are matched as a whole to the CSD0 of DRAM/SDRAM, the #CSD of MC9328MX1 is connected to the CS end of the 2 pieces of K4S281632, the CLK end of the 2 pieces of K4S281632 is connected to the SDCLK ​​end of MC9328MX1, the CLE end of the 2 pieces of K4S281632 is connected to the SDCKE end of MC9328MX1; the RAS, CAS, and WE ends of the 2 pieces of K4S281632 are connected to the RAS, CAS, SDWE end, 2 pieces of K4S281632 address bus [A08-A00] connect to MC9328MX1 [A10-A02]; 2 pieces of K4S281632 address bus [A10-A09] connect to MC9328MX1 [MA11-MA10]; 2 pieces of K4S281632 address bus [A11] connect to MC9328MX1 [A12]; 2 pieces BA1 and BA0 of K4S241632 are connected to the address bus [A14-A13] of MC9328MX1; [DQ15-DQ0] of the upper 16-bit chip is connected to the data bus [D31-D16] of MC9328MX1, and [DQ15-DQ0] of the lower 16-bit chip is connected to the data bus [D15-D0] of MC9328MX1; UDQM and LDQM of the upper 16-bit chip are connected to DQM3 and DQM2 of MC9328MX1 respectively, and UDQM and LDQM of the lower 16-bit chip are connected to DQM1 and DQM0 of MC9328MX1 respectively.

3.5 Serial Interface Circuit Design

MC9328MX1 provides a serial interface, using the RS-232 standard interface, which can be directly connected end-to-end in the short-distance communication system. However, since the logic level of the LVTTL circuit in the MC9328MX1 system does not match the RS-232 standard logic level, the signal level conversion must be performed for normal communication between the two. This system uses the MAX3221 level conversion circuit. Taking the RS-232 standard 9-pin D-type interface as an example, to complete the most basic serial communication function, only RXD (data reception), TXD (data transmission) and GND (ground) terminals are required. The serial interface circuit is shown in Figure 8.

3.6 JTAG Interface Circuit Design

JTAG technology is an embedded debugging technology. A special test circuit TAP (test access port) is encapsulated inside the chip. The internal nodes are tested and controlled through a dedicated JTAG test tool. Currently, most ARM devices support the JTAG protocol. The standard JTAG interface is 4-wire; TMS (test mode selection), TCK (test clock), TDI (test data serial input), TDO (test data serial output). There are two standards for connecting the JTAG interface, namely the 14-pin JTAG interface and the MC9328MX1 connection circuit. In this way, the design of the embedded minimum system based on MC9328MX1 is completed.