TQ210——S5PV210 interrupt system

An interruption means that when the CPU is executing a program, it encounters an abnormal situation that needs to be handled. The CPU stops the current program, saves the necessary parameters of the current program, and turns to handle these abnormal situations. After the processing is completed, the CPU returns to the interruption point of the current program and continues to execute the original program.

1. Exception vector table

2. Level 1 exception handling

#define pExceptionIRQ ( *((volatile unsigned long *)(0xD0037418)) )

pExceptionIRQ = (unsigned long)IRQ_handle;

IRQ_handle:    

                   sub lr, lr, #4 // Save the scene                    

   stmfdsp!, {r0-r12, lr}      

                   bl irq_handler // Jump to interrupt handling function

                   ldmfd sp!, {r0-r12,pc}^ // restore the scene

3.VICX

The S5PV210 has a total of 4 VICs (Vectored Interrupt Controllers), which are interconnected in a daisy chain manner to support up to 93 interrupt sources.

These interrupt sources provide interrupt services for system DMA, timers, peripherals, multimedia, audio, security and other modules.

The interrupt types include IRQ and FIQ, both of which are level 2 in interrupt processing.

The daisy-chained 4 TZICs and 4 VICs are designed to support 93 interrupt sources. In the trusted domain design, the TZIC provides a soft interrupt for the secure interrupt system. It provides secure control of the nFIQ interrupt and the interrupt controller masks the interrupt source on systems without a security margin (vic). The latter is used to generate the nIRQ signal.

Daisy Chain: A method of transmitting signals along a bus in which devices are connected in series and signals are passed from one device to the next. The daisy chaining method assigns priority to devices according to their electrical position on the bus.

4. Register

(1) IRQSTATUS interrupt status

(2) VICINTSELECT (interrupt type selection: irq or fiq)

How to ensure that FIQ has the best interrupt response speed?

<1> FIQ mode has more banked registers, so the time wasted on saving registers can be avoided after entering the FIQ ISR.

<2>, FIQ is at the end of the exception vector table, so the ISR can start directly at the end of the vector table without jumping elsewhere.

(3) VICINTENABLE/VICINTENCLEAR (interrupt enable/disable setting)

In the interrupt enable register, each bit represents an interrupt source. Writing 1 to the corresponding bit in the VICINTENABLE register enables the interrupt (writing 0 is invalid, and when reading, it returns 1 if the interrupt is enabled, and 0 if it is not enabled), while writing 1 to the corresponding bit in the VICINTENCLEAR register disables the interrupt (writing 0 is invalid).

In some other CPUs, there is only one INTENABLE register. Writing 1 enables interrupts, and writing 0 disables interrupts.

(4) ISR related

How to set up ISR:

The interrupt system of S5PV210 adopts the following ISR determination strategy

<1> Divide the 93 interrupt sources into 4 groups. The ISRs of each group form an array with the interrupt number as the array index.

<2> The first addresses of the four ISR arrays are stored in VICVECTADDR0~VICVECTADDR3 respectively.

When binding an ISR, you only need to put the ISR address written by the user into the position indexed by the interrupt number in the ISR array.

How to obtain ISR:

When an interrupt occurs and jumps to IRQ in the first-level exception vector table, the scene must be protected first, and then the corresponding ISR is entered for execution.

To obtain the corresponding ISR, you only need to read the VICADDRESS register. This is because the interrupt system of S5PV210 will automatically push the ISR corresponding to the current interrupt from ICVECTADDRx to VICADDRESSx. This saves us the trouble of confirming the interrupt number using the query method and improves the response speed of IRQ.

5. Interrupt handling

Interrupt handling process

<1>, hardware event occurs, SRCPENDING bit response hangs

<2>, determine whether to generate an interrupt pending INTPENDING according to the interrupt enable setting, and determine whether the interrupt type is IRQ or FIQ according to INTSELECT

<3>, in response to the interrupt, the CPU automatically jumps to the IRQ or FIQ exception entry according to the first-level exception vector table

<4> For IRQ, in the secondary interrupt table, judge according to INTNUM and jump to the corresponding ISR for execution

<5>, interrupt returns, and this interrupt event ends

How to use interrupts:

<1>, Global settings, including setting the first-level exception vector table, clearing all interrupt hangs, disabling all interrupt sources, etc.

<2>, Make specific settings for the interrupts to be used, including setting the interrupt type to IRQ/FIQ, interrupt enable, priority, etc.

<3>, Bind the interrupt handler so that it can jump to the correct ISR when the secondary interrupt is processed. 

<4> Set the interrupt enable bit to allow interrupts to occur.

      Differences in interrupt handling on different platforms: some platforms set the interrupt bit to 1, while others clear the interrupt bit to 0; the way to obtain the interrupt number (which means obtaining the interrupt ISR) during a secondary interrupt is different. These differences will affect the interrupt response speed of the platform.

6. External interrupt

External interrupts refer to interrupts from outside the SoC, as opposed to internal interrupts (interrupts from inside the SoC, i.e., interrupts generated by various internal peripherals, such as timer interrupts).

S5PV210 supports 32 channels of external interrupts, each of which has a corresponding GPIO to receive interrupt signals from the outside. There are five optional interrupt trigger modes: level (high, low), edge (rising edge, falling edge, Both).      

(1) EXT_INT_0_CON external interrupt control register

EXT_INT_x_CON (x = 0~3) is used to configure the trigger mode of 32 external interrupt channels.

(2) EXT_INT_0_MASK external interrupt enable/disable

EXT_INT_x_MASK (x=0～3) is used to enable/disable the corresponding external interrupt channel

(3) EXT_INT_0_PEND external interrupt pending register

EXT_INT_xPEND (x=0～3) is used to mark the external interrupt pending. Writing 1 to the corresponding bit can clear the interrupt pending.

6. External interrupt setting process

<1>, Global interrupt initialization

<2>, set the corresponding GPIO to XEINTx

<3>, Bind interrupt handler

<4>, set EXT_INT_x_CON to configure the trigger mode

<5>, write EXT_INT_x_PEND to clear the interrupt

<6>, set EXT_INT_x_MASK to enable the corresponding channel

<7>, finally enable the corresponding external interrupt channel

analyze:

1. When an interrupt hang occurs, the CPU automatically jumps to the IRQ entry address in the first-level exception vector table.

2. Get the corresponding ISR address through IRQSTATUS and VICADDRESS mechanism and start execution.

3. The internal content of ISR should include three parts:

(1) Valid isr, handle the task corresponding to the key

(2) Write any value to VICxADDR to clear the interrupt

(3) Write 1 to EXT_INT_x_PEND to clear the corresponding interrupt