Explanation of ARM Compact Memory TCM

　　About TCM

　　TCM: Abbreviation for Fastly Coupled Memory. OnChip Memory is added to compensate for the uncertainty of cache access. Some CPUs contain separate Instrument TCM/Data TCM. TCM is included in the address mapping space of the memory and can be accessed as fast memory. TCM uses physical addresses, and write access to TCM is controlled by the internal protection information of the MMU. When writing to a memory location in TCM, no external write occurs.

　　TCM is used to provide low-latency memory to the processor without the unpredictability that is characteristic of cache. You can use TCM to store important routines, such as interrupt handling routines or real-time tasks that need to avoid cache uncertainty. In addition, you can use TCM to save temporary register data, data types whose local attributes are not suitable for cache, and important data structures such as interrupt stacks.

　　ARM's RAM includes static RAM, dynamic RAM, TCM---tightly coupled memory (TCM: TIghtly Coup ledMemories).

　　TCM is a fixed-size RAM that is tightly coupled to the processor core, providing performance comparable to cache. The advantage over cache is that the program code can precisely control what functions or codes are placed where (in RAM). Of course, TCM will never be kicked out of main memory, so it will have a performance preset by the user, rather than a statistical performance improvement like cache.

　　Introduction to Compact Memory

　　Compact memory refers to a fast on-chip storage area that has the same performance as on-chip cache, but because the program has full control over compact memory, it is more predictable than a statistically multiplexed cache. This is a feature introduced by ARM5TE, the purpose of which is to use this fast storage area to improve the performance of certain key codes (such as interrupt handling functions) on the one hand, and to keep the storage access latency consistent on the other hand, which is required by real-time applications. ARM6 further standardizes TCM operations.

　　Application areas of TCM

　　Predictable real-time processing (interrupt processing), avoiding cache analysis (encryption algorithms), or simply improving performance (processor-side encoding and decoding), etc.

　　Like the Harvard cache structure, the instruction TCM and data TCM are separate. TCM can be used in two ways: as a fast cache and as a local memory.

　　Local Memory

　　At this time, TCM is used as a faster memory, just like ordinary RAM. Because the instruction segment is sometimes also the object of data access, the instruction TCM is actually an integrated instruction and data TCM. A blocking operation must be followed between the write operation to TCM and the subsequent dependent instructions on this write operation.

　　Smartcache

　　TCM can be configured to be used as a cache for external RAM, and the corresponding external RAM must also be set with a cacheable flag. If the cached external RAM can be shared by multiple processors, then whether TCM should be consistent with the shared data is not specified, but is determined by the specific implementation manufacturer.

　　The TCM is not automatically consistent with the contents of the cache, which means that the memory area mapped to the TCM must be an uncached area. If an address falls in both the cache and the TCM, the result of accessing this address is unpredictable. Another limitation is that each TCM must be configured to be disjoint.

　　TCM Configuration

　　Through CP15 registers 0, 1, and 9:

　　Register 0

　　Read register 0 of CP15, opcode2 is 2:

　　MRC p15， 0， Rd， C0， C0， 2

　　Returns the contents of the TCM status register, where bits 16-18 represent the number of data TCMs and bits 0-3 represent the number of instruction TCMs.

　　Register 1

　　Before ARM6, bits 16 and 18 of register 1 were used to enable data TCM and instruction TCM (ARM946, ARM966). Since ARM6 can use register 9 to control the enable status of each TCM, these two bits of register 1 are obsolete and should be set to 1.

　　Register No. 9

　　Each TCM has a TCM region register. Setting this register can set the base address and size of the TCM. Before setting the TCM region register, you need to set the TCM select register.

　　Here are the instructions to access these relevant registers:

　　ARM InstrucTIon TCM Region Register

　　MRC/MCR P15， 0， Rd， C9， C1， 0 Data TCM Region Register

　　MRC/MCR P15， 0， Rd， C9， C1， 1 Instruction/Unified TCM Region Register

　　MRC/MCR P15， 0， Rd， C9， C2， 0 TCM Selection Register

　　Structure of TCM region register:

　　Base Address （Physical Address）［31-12］ SBZ/UNP［11-7］ Size［6-2］ SC［1］ En［0］

　　in:

　　The En bit is the enable bit, which enables this TCM when set to 1;

　　The SC bit is set to indicate that this TCM is used as a smart cache, and cleared to indicate local memory;

　　The Size field is read-only and has the following meanings:

　　Size Memory Size Memory

　　filed size field size

　　0b00000 0K 0b01101 4M

　　0b00011 4K 0b01110 8M

　　0b00100 8K 0b01111 16M

　　0b00101 16K 0b10000 32M

　　0b00110 32K 0b10001 64M

　　0b00111 64K 0b10010 128M

　　0b01000 128K 0b10011 256M

　　0b01001 256K 0b10100 512M

　　0b01010 512K 0b10101 1G

　　0b01011 1M 0b10110 2G

　　0b01100 2M 0b10111 4G

　　Note that the TCM blocks configured by the TCM area register cannot intersect, otherwise the consequences are unpredictable.