STM8 FLASH registers-EEWORLD

FLASH Control Register 1 (FLASH_CR1)

Address offset value: 0x00
Reset value: 0x00

STM8_FLASH control register 1 (FLASH_CR1)

Position 7:4	Reserved bit, must remain 0
Bit 3	HALT: Power down in Halt mode This bit can be set or cleared by software. 0: When the MCU is in Halt mode, the FLASH is in power down mode 1: When the MCU is in Halt mode, the FLASH is in running mode
Bit 2	AHALT: Power down in active halt mode 0: FLASH is in power down mode when MCU is in active halt mode 1: FLASH is in running mode when MCU is in active halt mode
Bit 1	IE: FLASH interrupt enable 0: interrupt disabled 1: interrupt enabled. An interrupt is generated when the EOP or WR_PG_DIS bit in the FLASH_IAPSR register is set
Bit 0	FIX: Fixed programming time 0: When the memory has been erased, the programming time is half of the standard programming time (1/2 tprog), otherwise it is the standard programming time tprog. 1: The programming time is fixed to the standard programming time tprog.

FLASH Control Register 2 (FLASH_CR2)

Address offset value: 0x01
Reset value: 0x00

STM8_FLASH control register 2 (FLASH_CR2)

Bit 7	OPT: Write operation to option bytes This bit can be set or cleared by software. 0: Write operation to option bytes is disabled 1: Write operation to option bytes is enabled
Position 6	WPRG: Word Programming When the operation is completed, this bit is set or cleared by hardware. 0: Word Programming operation is disabled 1: Word Programming operation is enabled
Bit 5	ERASE(1): Block erase operation is completed. This bit is set or cleared by hardware. 0: Block erase operation is disabled 1: Block erase operation is enabled
Bit 4	FPRG(1): Fast Block Programming This bit is set or cleared by hardware when the operation is completed. 0: Fast Block Programming operation is disabled 1: Fast Block Programming operation is enabled
Bit 3: 1	Reserved bits
Bit 0	PRG: Standard Block Programming This bit is set or cleared by hardware when the operation is complete. 0: Standard Block Programming operation is disabled 1: Standard Block Programming operation is enabled

FLASH complementary control register 2 (FLASH_NCR2)

Address offset value: 0x02
Reset value: 0xFF

STM8_FLASH complementary control register 2 (FLASH_NCR2)

Bit 7	NOPT: Write operation to option bytes This bit can be set or cleared by software. 0: Write operation to option bytes is enabled 1: Write operation to option bytes is disabled
Position 6	NWPRG: Word Programming When the operation is completed, this bit is set or cleared by hardware. 0: Word Programming operation is enabled 1: Word Programming operation is disabled
Bit 5	NERASE: Block Erase When the operation is completed, this bit can be set or cleared by software. 0: Block Erase operation is enabled 1: Block Erase operation is disabled
Bit 4	FPRG(1): Fast Block Programming This bit is set or cleared by hardware when the operation is completed. 0: Fast Block Programming operation is disabled 1: Fast Block Programming operation is enabled
Bit 3: 1	Reserved bits
Bit 0	NPRG: Standard Block Programming This bit can be set or cleared by software when the operation is complete. 0: Standard Block Programming operation is enabled 1: Standard Block Programming operation is disabled

FLASH Protection Register (FLASH_FPR)

Address offset value: 0x03
Reset value: 0x00

STM8_FLASH protection register (FLASH_FPR)

Bit 7: 6	Reserved bit, must remain '0'
Bit 5: 0	WPB[5:0]: User boot code protection bits. These bits indicate the size of the user boot code, whose value is loaded from the UBC option byte at boot time. Please refer to the datasheet for details about the protection page section.

FLASH Complementary Protection Register (FLASH_NFPR)

Address offset value: 0x04
Reset value: 0xFF

STM8_FLASH complementary protection register (FLASH_NFPR)

Bit 7: 6	Reserved bit, must remain '1'
Bit 5: 0	NWPB[5:0]: User boot code protection bits. These bits indicate the size of the user boot code, whose value is loaded from the NUBC option byte at boot time. Please refer to the datasheet for details about the protection page section.

FLASH program memory unprotect register (FLASH_PUKR)

Address offset value: 0x08
Reset value: 0x00

STM8_FLASH program memory unprotect register (FLASH_PUKR)

Bit 7:0	PUK[7:0]: Main Program Memory Unlock Key This bit can be written by software (in any mode). When reading this register, the return value is 0x00. Please refer to the write operation of the main program area for more details on the main program area write protection mechanism.

DATA EEPROM deprotection register (FLASH_DUKR)

Address offset value: 0x0A
Reset value: 0x00

STM8_DATA EEPROM deprotection register (FLASH_DUKR)

Bit 7:0	DUK[7:0]: DATA EEPROM unlock key This bit can be written by software (in any mode). When reading this register, the return value is 00h. Please refer to the write operation of the DATA area for more details on the data area write protection release mechanism.

FLASH Status Register (FLASH_IAPSR)

Address offset value: 0x05
Reset value: 0x00

STM8_FLASH status register (FLASH_IAPSR)

Bit 7	Reserved bit, guaranteed by hardware to be forced to 0
Position 6	HVOFF: High voltage end mark 0: HV on, start real programming 1: HV off, high voltage end
Position 5:4	Reserved bit, guaranteed by hardware to be forced to 0
Bit 3	DUL: DATA EEPROM area unlock flag This bit is set by hardware and can be cleared by software by writing 0 to it. 0: DATA EEPROM area write protection enabled 1: DATA EEPROM area write protection can be unlocked by using the MASS key
Bit 2	EOP: Programming end (write or erase operation) flag 0: No EOP event occurs 1: EOP event occurs. If IE in FLASH_CR1 is 1, an interrupt will be generated
Bit 1	PUL: Fast program memory end flag This bit is set by hardware and can be cleared by software by writing 0 to it 0: Main program memory area write protection is enabled 1: Main program memory area write protection can be disabled by using the MASS key
Bit 0	WR_PG_DIS: Flag for attempting to write to a protected page This bit is set by hardware and can be cleared by software by reading this register 0: No WR_PG_DIS event occurs. 1: An attempt to write to a protected page occurs. If IE in FLASH_CR1 is 1, an interrupt will be generated

FLASH register map and reset value

For more information about STM8 register boundary addresses, please refer to the General Hardware Register Map section in the data sheet.

STM8_FLASH register mapping and reset value
(Table 6: STM8 FLASH register mapping and reset value)

Keywords：STM8 FLASH Register Reference address：STM8 FLASH registers