ATtiny2313 reset and interrupt handling

AVR has different interrupt sources. Each interrupt and reset has its own interrupt vector in the program space. All interrupt events have their own enable bit. When the enable bit is set and the global interrupt enable bit I in the status register is also set, an interrupt can occur.

The lowest address of the program memory area of ​​ATtiny2313 defaults to the reset vector and interrupt vector. For a complete list of vectors, please refer to P40 "Interrupts". The list also determines the priority of the different interrupts. The lower the address of the vector, the higher the priority. RESET has the highest priority, and the second is INT0 - External Interrupt Request 0.

When any interrupt occurs, the global interrupt enable bit I is cleared to 0, thereby disabling all other interrupts. User software can set I in the interrupt routine to achieve interrupt nesting. In this case, all interrupts can interrupt the current interrupt service routine. I is automatically set after executing the RETI instruction.

There are basically two types of interrupts. The first is triggered by an event and sets the interrupt flag. For these interrupts, the program counter jumps to the actual interrupt vector to execute the interrupt handler, and the hardware will clear the corresponding interrupt flag. The interrupt flag can also be cleared by writing "1" to it. When an interrupt occurs, if the corresponding interrupt enable bit is "0", the interrupt flag is set and remains set until the interrupt is executed or cleared by software. Similarly, if the global interrupt flag is cleared, all interrupts that have occurred will not be executed until I is set. The pending interrupts are then executed in order of interrupt priority. 

The second type of interrupt will always be triggered as long as the interrupt condition is met. These interrupts do not require an interrupt flag. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

After exiting an interrupt, the AVR always returns to the main program and executes at least one instruction before executing other pending interrupts. It should be noted that the status register is not automatically saved when entering the interrupt service routine, nor is it automatically restored when the interrupt returns. This must be done by the user through software. When the CLI instruction is used

to disable interrupts, the interrupt disable takes effect immediately. No interrupt can occur after the CLI instruction is executed, even if it occurs at the same time as the CLI instruction is executed. The following example shows how to use this instruction to prevent interrupts from occurring when writing to the EEPROM to avoid possible corruption of the EEPROM contents.

Assembly code routine
in r16, SREG ; save SREG
cli ; disable interrupts
sbi EECR, EEMWE ; start EEPROM write operation
sbi EECR, EEWE
out SREG, r16 ; restore SREG (I bit)

C code routine
char cSREG;
cSREG = SREG; /* Save SREG */
/* Disable interrupts */
_CLI();
EECR |= (1<EECR |= (1<SREG = cSREG; /* Restore SREG (I bit) */

When using SEI instruction to enable interrupts, the first instruction following it will be executed first before any interrupt is executed. 

Assembly code routine
sei ; Set global interrupt enable flag
sleep ; Enter sleep mode and wait for interrupt to occur
; Note: MCU will enter sleep mode first before executing any pending interrupt

C code routine
_SEI(); /* Set global interrupt enable flag */
_SLEEP(); /* Enter sleep mode and wait for interrupt to occur */
/* Note: MCU will enter sleep mode first before executing any pending interrupt */

The AVR interrupt response time is at least 4 clock cycles. After 4 clock cycles, the program jumps to the actual interrupt handling routine. During these 4 clock cycles, the PC is automatically pushed onto the stack. In general, the interrupt vector is a jump instruction, which requires 3 clock cycles. If the interrupt occurs during the execution of a multi-clock cycle instruction, the MCU will execute the interrupt program only after the multi-cycle instruction is executed. If the MCU is in sleep mode when the interrupt occurs, the interrupt response time will increase by 4 clock cycles. In addition, the startup time required for different sleep modes must be considered. This time is not included in the clock cycle mentioned above.

The interrupt return requires 4 clocks. During this period, the PC (two bytes) will be popped off the stack, the stack pointer will be incremented by two, and the I bit of the status register SREG will be set.