Introduction to ARM processors

The concept of ARM

ARM (Advanced RISC Machine) can be considered as the name of a company, a general term for a type of microprocessor, or the name of a technology.

ARM does not manufacture or sell chips, it only sells chip technology licenses. Its partner companies match various hardware components, such as UART, SDI, I2C, etc., to design different SoC chips according to different needs.

Application scenarios of ARM

ARM-based processors have the advantages of high speed, low power consumption and low price and are widely used in the following fields:

Provide an open application platform that can run complex operating systems for products such as communications, consumer electronics, and imaging equipment;

Provide real-time embedded applications in the fields of mass storage, automotive electronics, industrial control and network applications;

Security systems, such as credit cards, SIM cards, etc.

Technical characteristics of ARM

The ARM architecture supports the 32-bit ARM instruction set and the 16-bit Thumb instruction set (greatly reducing the storage space of the code).

Here is an example to explain the characteristics between architecture, core, processor and chip: S3C2440, this is a SoC chip, note that it is not a CPU.

2440 is somewhat similar to the 51 single-chip microcomputer we are familiar with. Both are embedded. The development of embedded has gone through three stages so far, namely SCM, MCU, and SoC.

51 belongs to SCM or MCU, while 2440 belongs to SoC. Let’s first take a look at the internal structure of the 51 microcontroller.

Its internal structure can be simply divided into two parts: CPU and peripherals. Let's take a look at the internal structure of 2440: the arm920t in the middle is its processor. In my opinion, processor and core are the same concept here, but one is a hard concept and the other is a soft concept. The 920t here is both a processor and a core. What Samsung does is everything else except this CPU.

ARM version series

ARM version I: V1 architecture.

This version of the architecture only appeared in the prototype ARM1, had only 26 bits of addressing space, and was not used in commercial products.

Its basic properties are:

Basic data processing instructions (no multiplication);

Byte, halfword and word based Load/Store instructions;

Transfer instructions, including subroutine call and link instructions;

Software interrupt instruction SWI for use by the operating system; Addressing space: 64MB (226).

ARM version II: V2 architecture

This version of the architecture extends the V1 version, such as the ARM2 and ARM3 (V2a) architectures. It includes support for 32-bit multiplication instructions and coprocessor instructions. Version 2a is a variant of version 2. The ARM3 chip uses version 2a and is the first ARM processor to use on-chip cache. It also has a 26-bit address space and is now obsolete.

Compared with version V1, the V2 architecture adds the following features:

Multiplication and multiply-accumulate instructions;

Support coprocessor operation instructions;

Fast interrupt mode;

The most basic memory and register exchange instructions of SWP/SWPB;

Addressing space: 64MB.

ARM version III: V3 architecture

ARM's first microprocessor designed as an independent company in 1990 was version 3 of the ARM6. It is available as an IP core, an independent processor, and an integrated CPU with on-chip cache, MMU, and write buffer. Variant versions include 3G and 3M. Version 3G is a version 3 that is not forward compatible with version 2a. Version 3M introduces signed and unsigned multiplication and multiply-add instructions that produce full 64-bit results.

The V3 architecture (currently deprecated) made significant changes to the ARM architecture:

The addressing space is increased to 32 bits (4GB);

The current program status information is moved from the original R15 register to the current program status register CPSR (Current Program Status Register);

Added the program status save register SPSR (Saved Program Status Register);

Added two exception modes to make it easier for operating system code to use data access abort exceptions, instruction prefetch abort exceptions, and undefined instruction exceptions;

Added MRS/MSR instructions to access the newly added CPSR/SPSR registers;

Added the ability to return from exception handling.

ARM version IV: V4 architecture

The V4 architecture is a further expansion of the V3 architecture. The V4 architecture is currently the most widely used ARM architecture, and ARM7, ARM8, ARM9 and StrongARM all use this architecture. V4 no longer requires compatibility with the 26-bit address space, and also clarifies which instructions will cause undefined instruction exceptions.

The following features have been added to the instruction set:

Signed and unsigned half-word and signed byte store/retrieve instructions;

Added T variant, the processor can work in Thumb state, and added 16-bit Thumb instruction set;

Improved the function of software interrupt SWI instruction;

The processor system mode uses user register operations when privileged mode is introduced;

Capture some unused instruction space as undefined instructions

ARM version V: V5 architecture

The V5 version of the architecture adds some new instructions based on the V4 version. Both ARM10 and Xscale use this version of the architecture.

The new commands are:

BLX instruction for transfer with link and exchange;

Count leading zeros CLZ instruction;

BRK interrupt instruction;

Added digital signal processing instructions (V5TE version);

Add more optional instructions to the coprocessor;

Improved the switching efficiency between ARM/Thumb states;

E—Enhanced DSP instruction set, including all arithmetic operations and 16-bit multiplication operations;

J----Supports the new JAVA and provides hardware and optimized software acceleration functions for byte code execution.

ARM version VI: V6 architecture

The V6 architecture was released in 2001 and was first used in the ARM11 processor released in the spring of 2002. While reducing power consumption, it also enhanced graphics processing performance. By adding SIMD (Single Instruction, Multiple Data) functions for effective multimedia processing, the voice and image processing functions were increased to four times that of the prototype.

This architecture adds the following features based on version V5:

THUMBTM: 35% code compression;

DSP expansion: high-performance fixed-point DSP functions;

JazelleTM: Java performance optimization, can improve 8 times;

Media expansion: audio/video performance optimization, can be improved by 4 times

ARM Version VⅡ: V7 Architecture

The V7 architecture was born on the basis of the ARMv6 architecture. This architecture uses Thumb-2 technology, which is developed based on ARM's Thumb code compression technology and maintains complete code compatibility with existing ARM solutions.

Thumb-2 technology uses 31% less memory than pure 32-bit code, reducing system overhead, and can provide 38% higher performance than existing Thumb-based solutions.

The ARMv7 architecture also uses NEON technology, which increases DSP and media processing capabilities by nearly 4 times, and supports improved floating-point operations to meet the needs of next-generation 3D graphics, game physics applications, and traditional embedded control applications. In addition, ARMv7 also supports an improved operating environment to cater to the increasing use of JIT (Just In Time) and DAC (Dynamic Adaptive Compilation) technologies.

ARM Version VIII: V8 Architecture

This is a new IP core designed for high-performance embedded signal processing applications. The v8 architecture is developed on the 32-bit ARM architecture and will be first used in product areas that have higher requirements for extended virtual address and 64-bit data processing technology, such as enterprise applications and high-end consumer electronics.

The ARMv8 architecture consists of two execution states: AArch64 and AArch32. The AArch64 execution state introduces a new instruction set A64 for 64-bit processing technology, while the AArch32 execution state will support the existing ARM instruction set.

The main features of the current ARMv7 architecture will be retained or further expanded in the ARMv8 architecture, such as TrustZone technology, virtualization technology, and NEON advanced SIMD technology, etc.
The left side is the architecture, and the right side is the processor, also called the core. ARM's first and most successful CPU is ARM7TDMI, which is based on ARMv4. The ARM architecture includes the following RISC features:

Read/Store Architecture

Unaligned memory access is not supported (ARMv6 kernel now supports it)

Orthogonal instruction set (Orthogonal instruction set)

A large 16 × 32-bit register file

The fixed 32-bit operation code (opcode) length reduces the cost of encoding and reduces the burden of decoding and pipelining.

Most of them are executed in one CPU cycle. Different versions of the architecture may have some adjustments.

Like Samsung, other major manufacturers that cooperate with ARM usually put their CPU and various peripheral IPs together, and then take the drawings to tape out the chips. The product is also a square with many pins underneath. This thing not only includes the CPU, but also other controllers. This thing is called SOC (system on chip). From the English point of view, the so-called quad-core SOC does not refer to the CPU alone, but the quad-core system.

So what major manufacturers are doing now is to buy ARM's authorization, get the source code of the ARM processor, and then make some peripheral IPs (either buy or design them by themselves), form a SOC, and then go to tape-out. Different SOCs have different architectures (that is, how the CPU is connected to the IP, some are based on the bus, and some are based on DDR), so HiSilicon has its own SOC architecture. However, no matter which manufacturer, no matter how much they try, they have never touched the CPU. The ARM core stays there, that is, the central processing unit. Cortex series processors