For large project files containing nios, timing constraints, and layout and routing, modify the internal module names and some variable names.

FPGA菜鸡

For large project files containing nios, timing constraints, and layout and routing, modify the internal module names and some variable names. [Copy link]

I modified the internal module names and some variable names of a large project file containing nios, timing constraints, and layout and routing. After compiling and synthesizing, a lot of problems occurred. Which files can be modified to solve these problems? Please give me some ideas. I have unified the variable names in the qsf and tcl files, but errors still occur. I am very anxious.

FPGA菜鸡

What aspects need to be modified to solve it?

Jacktang

It is key to prepare a flowchart in advance. When you encounter problems, go back to the flowchart and make sure you don’t go wrong in the direction.

How to modify its internal module name and some variable names is a technical issue