Detailed description of I2C bus protocol and timing, getting started is no longer difficult

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Detailed description of I2C bus protocol and timing, getting started is no longer difficult [Copy link]

In life, we often encounter power failures in devices, such as mobile phones, smart bracelets, computers, etc. However, the stored information will not be lost, such as phone numbers, text messages, notes, WeChat, QQ information, etc. will all be saved; these things will disappear after restoring the factory settings;
this is because these devices have a "power-off save" device, such as hard disks, USB flash drives, etc. Their characteristics are that after the power is off, the information stored on them will not be lost, just like the human brain, which has a memory function. This kind of device is
also very common in the industrial field, generally EEPROM and FLASH. The common point between the two is that they are readable and writable, and can be saved when the power is off;
the difference is that EEPROM does not need to be erased before writing, while FLASH must be erased before writing, otherwise the writing will not be successful; EEPROM generally uses the I2C bus to communicate, while FLASH generally uses the SPI bus.

EEPROM memory system architecture diagram

Today I will talk to you about the I2C bus :

Bit transfer

The I2C bus is a bidirectional two-wire synchronous serial bus developed by Philips to achieve effective control between ICs. It only needs two wires (SDA and SCL) to transmit information between devices connected to the bus.

The I2C bus transmits data in bits. SCL is the clock line and SDA is the data line. When the SCL clock line is high, the level on the SDA data line is not allowed to be modified. When the SCL clock line is low, the level on the SDA data line can be high or low.

I2C bus bit transmission

Start condition : When SCL is high, SDA switches from high to low, indicating the start of data transmission.
Stop condition : When SCL is high, SDA jumps from low to high, indicating the end of data transmission.
Idle condition : When the SDA and SCL signal lines of the I2C bus are both high at the same time, indicating the idle state.

Start and stop conditions

Data Transfer

Byte transfer

When sending data, the host first sends a start signal, then switches the SDA signal to output mode, and then sends out 8 bits of data in sequence from high to low;
after the sending is completed, the host switches the SDA signal to input mode and waits for the slave to respond with ACK or NAK; then sends the next data

I2C bus data transmission

Congji Address

In the I2C bus system, each device has its fixed address, which is generally determined by the chip's A0, A1, and A2. The device address byte consists of seven address bits (D7-D1) and a direction bit (D0).
The device address's D7-D4 is generally fixed to 1111 by the manufacturer, and the remaining D3, D2, and D1 are connected to the chip's A2, A1, and A0; D0 is 0x00 for write, and D0 is 0x01 for read. This is why you see 0xA0 and 0xA1 in the example code.

EEPROM device address

Reading and Writing Process

1. Data writing process

1. The host sends an I2C bus stop signal to prevent the bus from being busy and failing to write data

2. The host sends an I2C bus reset signal to ensure that the bus is idle before writing data

3. The host sends an I2C bus start signal to start writing data

4. The host sends the I2C cluster address and write mode (W/R=0) signal, and waits for a cluster response signal

5. After the host receives the ACK response signal, it starts writing multiple bytes. After writing each byte, it needs to wait for a response signal from the slave.

6. After the host receives the ACK response signal, it sends a 2IC bus stop signal to ensure that the bus is in an idle state

2. Data reading process

1. The host sends an I2C bus stop signal to prevent the bus from being busy and failing to write data

2. The host sends an I2C bus reset signal to ensure that the bus is idle before reading data

3. The host sends an I2C bus start signal to start a data read

4. The host sends the I2C cluster address and read mode (W/R=1) signal, and waits for a cluster response signal

5. After the host receives the ACK response signal, it starts reading multiple bytes. After each byte is read, it needs to send an ACK response signal to the slave.

6. After the host receives the ACK response signal, it sends the I2C bus stop signal to ensure that the bus is in an idle state

Host read/write data process

Conclusion

The I2C bus is very common in embedded applications, and almost all power electronic devices use this bus.

Based on my many years of work experience, I have recorded my understanding of it. If there is anything wrong, I hope you can point it out. Today's I2C bus will be written here first. I hope you like it.

freebsder

Thanks for sharing. I've been working on smbus recently. It's similar to i2c and has many uses.