About the setting and rescue methods of AVR microcontroller fuse bits

Fuse bits are a unique feature of ATMEL's AVR microcontrollers. Each model of AVR microcontroller has some fuse bits with specific meanings, and its characteristics are shown as multiple erasable E²PROM. By configuring (programming) these fuse bits, users can set some features, parameters, and I/O configurations of AVR in a fixed manner, and of course also lock (encrypt) the running code in the chip.

Users can configure the fuse bits of AVR using parallel programming, ISP programming, and JTAG programming, but different programming tools provide different ways to configure the fuse bits (referring to the human-machine interface). Some are by directly filling in the fuse bit values ​​(such as: CVAVR, PonyProg2000 and SLISP, etc.), and some are by listing table selection (such as AVR STUDIO, BASCOM-AVR). The former program interface is relatively simple, but users need to carefully query the operation, which will cause some unexpected consequences, such as causing the chip to fail to operate normally and unable to enter the ISP programming mode again. It is recommended that users choose programming software with a user table selection interface when configuring the fuse bits of AVR, such as BASCOM-AVR. However, the moderator uses the former PonyProg2000. The configuration operation of the AVR fuse bits is a relatively delicate work, and users often ignore its importance or find it difficult to master. Seeing that so many people do not know how to use and misoperate the fuse bits of AVR, combined with my own use practice, I give the following opinions and references. The following are some key points and related matters that need to be paid attention to when configuring the AVR fuse bits, as well as the corresponding rescue methods.

1.1.1 Correctly configure the AVR fuse bit The configuration of the AVR fuse bit is a delicate task, and users often overlook its importance or find it difficult to master. Here are some key points and related matters that need to be paid attention to when configuring the AVR fuse bit. For the specific definition and function of the ATmega128 fuse bit, please refer to the relevant chapters of this book. A complete summary table will be given in the appendix.

(1) In the AVR device manual, the fuse bit is defined as programmed (Programmed) and unprogrammed (Unprogrammed). "Unprogrammed" means the fuse state is "1" (disabled); "Programmed" means the fuse state is "0" (enabled). Therefore, the process of configuring the fuse bit is actually "configuring the fuse bit to be unprogrammed state "1" or programmed state "0"".

(2) When using programming tool software that allows you to determine the fuse bit status value by checking the box, please first read the software instructions carefully to understand whether "√" means setting the fuse bit status to "0" or "1".

(3) When using the programming download program in CVAVR, special attention should be paid. Since the initial state of most fuse bits is defined as "1" when the CVAVR programming download interface is initially opened, do not use the "all" option in its programming menu options. At this time, the "all" option will configure the fuse bits of the chip according to the initial state definition of the fuse bits, but in fact it is often not the configuration result required by the user. If you want to use the "all" option, you should first use "read->fuse bits" to read the actual state of the fuse bits in the chip, and then use the "all" option.

(4) Before using a new AVR chip, you should first check the configuration of its fuse bits, then configure the fuse bits according to actual needs, and record the status of each fuse bit for filing.

(5) After the AVR chip is encrypted, only the data in the internal Flash and E2PROM of the chip cannot be read. The status of the fuse bits can still be read, but the configuration cannot be modified. The chip erase command clears the data in the Flash and E2PROM, and at the same time configures the status of the two lock bits to "11", which is in an unlocked state. However, the chip erase command does not change the status of other fuse bits.

(6) The correct operation procedure is: when the chip is unlocked, download the running code and data, configure the relevant fuse bits, and finally configure the chip lock bits. After the chip is locked, if the fuse bits are found to be incorrectly configured, the chip erase command must be used to clear the data in the chip and unlock it. Then re-download the running code and data, modify the configuration-related fuse bits, and finally configure the chip lock bits again.

(7) When using ISP serial download programming, the SPIEN fuse bit should be configured to "0". The default state of the SPIEN bit when the chip leaves the factory is "0", indicating that ISP serial download data is allowed. Only when this bit is in the programmed state "0" can ISP download be performed through the SPI port of the AVR. If this bit is configured as unprogrammed "1", ISP serial download data is immediately prohibited. At this time, the SPIEN state can only be reset to "0" through parallel mode or JTAG programming to open ISP. Under normal circumstances, the SPIEN state should be kept at "0". Allowing ISP programming will not affect the I/O function of its pins, as long as the ISP interface and the devices connected in parallel are isolated when designing the hardware circuit, such as using series resistors or circuit breaker jumpers.

(8) When your system does not use the JTAG interface for download programming or real-time online simulation debugging, and the pins of the JTAG interface need to be used as I/O ports, the fuse bit JTAGEN must be set to "1". The JTAGEN state of the chip is "0" by default when it leaves the factory, indicating that the JTAG interface is allowed and the external pins of JTAG cannot be used as I/O ports. When the JTAGEN state is set to "1", the JTAG interface is immediately disabled. At this time, JTAG can only be reset to "0" and JTAG can only be opened through parallel mode or ISP programming.

(9) In general, do not set the fuse to define the RESET pin as I/O (such as setting the ATmega8 fuse RSTDISBL to "0"). This will cause the ISP download programming to be unable to proceed, because before entering the ISP mode programming, the RESET pin needs to be pulled low to put the chip into the reset state first.

(10) When using an AVR chip with an internal RC oscillator, pay special attention to the configuration of the fuse bit CKSEL. Generally, the default state of the CKSEL bit when the chip leaves the factory is to use the internal 1MHz RC oscillator as the system clock source. If you use an external oscillator as the system clock source, do not forget to correctly configure the CKSEL fuse bit first, otherwise the timing of your entire system will be problematic. When your design does not use an external oscillator (or a specific oscillation source) as the system clock source, do not misoperate or mistakenly configure the CKSEL fuse bit to use an external oscillator (or other different types of oscillation sources). Once this happens, the chip cannot be operated using the ISP programming method (because the ISP method requires the chip's system clock to work and generate timing control signals), and the chip looks "broken". At this time, the only way to save it is to remove the chip and use the parallel programming method, or use the JTAG method (if JTAG is allowed and there is a JTAG interface on the target board). Another way to solve the problem is to try to temporarily add different types of oscillation clock signals to the crystal pins of the chip. Once the ISP can operate the chip, immediately configure CKSEL to use the internal 1MHz RC oscillator as the system clock source, and then reconfigure CKSEL correctly according to the actual situation.

(11) When using an AVR chip that supports IAP, if you do not use the BOOTLOADER function, be careful not to set the fuse bit BOOTRST to "0", as it will cause the chip to not start executing the program from 0x0000 of the Flash when it is powered on. The default state of the BOOTRST bit is "1" when the chip leaves the factory. For the configuration of BOOTRST, the design of the BOOTLOADER program, and the application of IAP, please refer to the relevant content in this chapter.

1.1.2 Configuration of important fuse bits in ATmega128 The previous section introduced the key points and precautions for configuring AVR fuse bits. This section explains the configuration of several important fuse bits when using ATmega128 under normal circumstances.

(1) Fuse bit M103C. The configuration of M103C will set whether the ATmega128 works in ATmega103 compatible mode or in ATmega128 native mode. The default state of M103C is "0" when the ATmega128 leaves the factory, that is, it works in ATmega103 compatible mode by default. When the user system design makes the chip work in ATmega128 mode, the state of M103C should be configured to "1" first.

(2) CLKSEL0..3. CLKSEL0, CLKSEL1, CLKSEL2, and CLKSEL3 are used to select the clock source of the system. There are five different types of clock sources to choose from (each type has finer divisions). The default settings of the chip when it leaves the factory are "0001" for CLKSEL3..0 and "10" for SUT1..0, respectively. That is, the internal 1MHz RC oscillator is used with the longest startup delay. This ensures that the initial ISP download can be performed regardless of whether the external oscillation circuit is working. Be very careful when rewriting the CLKSEL3..0 fuse bit, because if the rewriting is wrong, the chip will not be able to start, see the explanation in point 10 of the previous section.

(3) JTAGEN. If the JTAG interface is not used, the status of JTAGEN should be set to "1", that is, JTAG is disabled and the JTAG pins are used as I/O ports.

(4) SPIEN. SPI mode downloading of data and programs is allowed, and the default state is "0". Generally, its state is retained.

(5) WDTON. The watchdog timer is always on. WDTON defaults to "1", which means that the watchdog timer is always disabled. If this bit is set to "0", the watchdog timer will always be on and cannot be controlled by the internal program. This is designed to prevent unknown code from turning off the watchdog timer by writing to the register when the program runs away (although turning off the watchdog timer requires a special method, it ensures higher reliability).