Briefly describe the AVR microcontroller timer

AVR timer key points introduction

The M16's T1 16-bit timer has a total of 15 operating modes. The other two 8-bit timers (T0/T2) are relatively simple, except that T2 has an asynchronous operating mode for RTC applications.

(Overflow interrupt and compare match interrupt can be used as timing function)

5 types of work

1 Normal mode WGM1=0

Similar to the normal mode of 51, there is a TOV1 overflow interrupt, which occurs at TOP

1 Use internal counting clock for ICP capture input occasions --- measure pulse width/infrared decoding

(The capture input function can work in multiple modes, not just normal mode)

2 Use external counting pulse input for counting and frequency measurement

For other applications, it is more convenient to use other modes, and you don’t need to worry about it like 51

2 CTC mode [clear timer mode on compare match] WGM1=4,12

It is similar to the automatic reload mode of 51.

1 Used to output a square wave signal with a 50% duty cycle

2 Used to generate accurate continuous timing signals

When WGM1=4, the maximum value is set by OCR1A, and OCF1A compare match interrupt is generated at TOP

When WGM1=12, the maximum value is set by ICF1, and an ICF1 input capture interrupt is generated at TOP

Note: When WGM=15, OC1A can also output square waves, and has double buffering function.

Calculation formula: fOCn=fclk_IO/(2*N*(1+TOP))

The variable N represents the pre-scaling factor (1, 8, 32, 64, 256, 1024).

3 Fast PWM mode WGM1=5,6,7,14,15

Single ramp counting, used to output high frequency PWM signal (twice the frequency of double ramp)

There is a TOV1 overflow interrupt, which occurs when TOP

After compare match, OCF1x compare match interrupt can be generated.

When WGM1=5, the maximum value is 0x00FF, 8-bit resolution

When WGM1=6, the maximum value is 0x01FF, 9-bit resolution

When WGM1=7, the maximum value is 0x03FF, 10-bit resolution

When WGM1=14, the maximum value is set by ICF1, and an ICF1 input capture interrupt is generated at TOP (single buffer)

When WGM1=15, the maximum value is set by OCR1A, and OCF1A compare match interrupt is generated at TOP (double buffering, but OC1A will not have PWM capability and can only output square waves at most)

When changing the TOP value, it must be ensured that the new TOP value is not less than the value of all comparison registers.

Note that even if OCR1A/B is set to 0x0000, a narrow pulse of one timer clock cycle will be output instead of being low all the time.

Calculation formula: fPWM = fclk_IO / (N * (1 + TOP))

4 Phase correction PWM mode WGM1=1,2,3,10,11

Dual ramp counting for outputting high-precision, phase-accurate, symmetrical PWM signals

There is a TOV1 overflow interrupt, but it occurs during BOOTOM

After compare match, OCF1x compare match interrupt can be generated.

When WGM1=1, the maximum value is 0x00FF, 8-bit resolution

When WGM1=2, the maximum value is 0x01FF, 9-bit resolution

When WGM1=3, the maximum value is 0x03FF, 10-bit resolution

When WGM1=10, the maximum value is set by ICF1, and an ICF1 input capture interrupt is generated at TOP (single buffer)

When WGM1=11, the maximum value is set by OCR1A, and OCF1A compare match interrupt is generated at TOP (double buffering, but OC1A will not have PWM capability and can only output square waves at most)

When changing the TOP value, it must be ensured that the new TOP value is not less than the value of all comparison registers.

Can output PWM signal with 0%~100% duty cycle

If you want to change the TOP value while T/C is running, it is best to use the phase and frequency correction mode instead of the phase correction mode. If TOP remains unchanged, there is actually no difference between these two operating modes.

Calculation formula: fPWM = fclk_IO / (2*N*TOP)

5 Phase and frequency correction PWM mode WGM1=8,9

Dual ramp counting for outputting high-precision PWM waveforms with accurate phase and frequency

There is a TOV1 overflow interrupt, but it occurs during BOOTOM

After compare match, OCF1x compare match interrupt can be generated.

When WGM1=8, the maximum value is set by ICF1, and an ICF1 input capture interrupt is generated at TOP (single buffer)

When WGM1=9, the maximum value is set by OCR1A, and OCF1A compare match interrupt is generated at TOP (double buffering, but OC1A will not have PWM capability and can only output square waves at most)

The main difference between the phase-frequency correction PWM mode and the phase-correction PWM mode is the update time of the OCR1x register.

When changing the TOP value, it must be ensured that the new TOP value is not less than the value of all comparison registers.

Can output PWM signal with 0%~100% duty cycle

When using a fixed TOP value, it is best to use the ICR1 register to define TOP. In this way, OCR1A can be used to output PWM waves on OC1A.

However, if the PWM base frequency is constantly changing (by changing the TOP value), the double buffering feature of the OCR1A makes it more suitable for this application.

Calculation formula: fPWM = fclk_IO / (2*N*TOP)

Clock source of T/C

The clock source of T/C can be selected in many ways, controlled by CS12:0, and used for high speed (low frequency division)/long time (high frequency division)/external counting occasions respectively.

A 16-bit timer, driven by an 8MHz system clock, can achieve uS-level high-speed timing and ultra-long timing of up to 8 seconds, which is the weakness of the standard 51

CS12 CS11 CS10 Description

0 0 0 No clock source (T/C stopped)

0 0 1 clkIO/1 (no prescaler)

0 1 0 clkIO/8 (from prescaler)

0 1 1 clkIO/64 (from prescaler)

1 0 0 clkIO/256 (from prescaler)

1 0 1 clkIO/1024 (from prescaler)

1 1 0 External T1 pin, falling edge drive

1 1 1 External T1 pin, rising edge drive

Divider reset

In high prescaler applications, resetting the prescaler to synchronize the T/C and program operation can reduce errors.

However, you must pay attention to whether another T/C is also using this prescaler, because resetting the prescaler will affect all T/Cs connected to it.

External clock source

Due to the use of pin synchronization logic, it is recommended that the maximum frequency of the external clock should not be greater than fclk_IO/2.5.

The external clock source is not fed into the prescaler

After selecting to use an external clock source, even if the T1 pin is defined as an output, the logic signal level change on the T1 pin will still drive the T/C1 count. This feature allows the user to control the count through software.

Input Capture Unit

The input capture unit of the T/C can be used to capture external events and assign a time stamp to indicate the moment of occurrence.

The trigger signal of external event is input by pin ICP1, and can also be realized by analog comparator unit.

Time stamps can be used to calculate frequency, duty cycle, and other characteristics of a signal, as well as to create a log of events.

The input capture unit can work in multiple working modes

(When the waveform generation mode (WGM1 = 12, 14, 10, 8) of TOP is defined using ICR1, ICP1 is disconnected from the input capture function, so the input capture function is disabled.)

It is not recommended to change the TOP value during operation in any input capture operating mode.

When the logic level (event) on pin ICP1 changes, or the analog comparator output ACO changes, and this level change is confirmed by the edge detector, the input capture is triggered:

The 16-bit TCNT1 data is copied to the input capture register ICR1, and the input capture flag ICF1 is set.

If ICIE1 = 1 at this time, the input capture flag will generate an input capture interrupt.

ICF1 is automatically cleared when an interrupt is executed, or it can be cleared by software by writing a logic 1 to its corresponding I/O location.

Note that changing the trigger source may cause an input capture. Therefore, after changing the trigger source, the input capture flag must be cleared to avoid erroneous results.

Except for the waveform generation mode that uses ICR1 to define TOP, the noise suppressor and edge detector in the T/C are always enabled.

(Actually, it is always enabled??)

When the noise suppressor is enabled, additional logic is added before the edge detector and a delay of 4 system clock cycles is introduced.

The noise suppressor uses the system clock and is therefore not affected by the prescaler

When using input capture interrupt, the interrupt routine should read the ICR1 register as early as possible.

If the processor does not read the data of ICR1 before the next event occurs, ICR1 will be overwritten by the new value and the correct capture result cannot be obtained.

Measuring the duty cycle of an external signal requires changing the trigger edge after each capture.

Therefore, the sensitive signal edge must be changed as soon as possible after reading ICR1. After changing the edge, ICF1 must be cleared by software (write 1" at the corresponding I/O location).

If only frequency measurement is required and interrupt generation is used, there is no need to clear ICF1 by software.

Output Compare Unit

The 16-bit comparator continuously compares the contents of TCNT1 and OCR1x. Once they are found to be equal, the comparator immediately generates a match signal.

Then OCF1x is set at the next timer clock.

If OCIE1x = 1 at this time, setting OCF1x will cause an output compare interrupt.

(That is to say, the output comparison can work in all working modes, but it is more useful and more powerful in PWM mode)

One of the properties of the output compare unit A (OCR1A) is that it defines the TOP value of the T/C (ie the resolution of the counter).

The TOP value is also used to define the period of the waveform produced by the waveform generator.

Since writing TCNT1 in any mode will prevent a compare match on the next timer clock cycle, there is a risk of changing TCNT1 when using output compare, regardless of whether the Timer/Current Clock is running.

This feature can be used to initialize OCR1x to the same value as TCNT1 without triggering an interrupt.

Forced Output Compare (FOC)

When operating in non-PWM mode, a compare match can be generated by writing "1" to the forced output compare bit FOC1x.