STM8S103F3--PWM configuration

The chip used in this article is stm8s103f3.

The following mainly describes the process of configuring TIM2 channel 1 for PWM output.

1. Register configuration

4-bit prescaler, the counter count frequency Fck_cnt = Fck_psc/2^(PSC[3:0]) = 16M/2^0 = 16M

Then the counting period is 1/16us, which means the counter will count once every 1/16us.

TIM2_PSCR=0x00; //Division value=0 16M

Auto-reload register,

When the auto-reload register = 0, the counter is in a blocked state, that is, it is not counting. Because when CNTR = ARR, CNTR will be cleared, so the auto-reload register should be greater than 0 during configuration. In addition, the value of the auto-reload register is the period of the PWM waveform. For example, if ARR = 0X0100, the period of PWM is 0x0100*1/16=16us, and the period of PWM is 16us.

  TIM2_ARRH=0x01; //Automatically reload the value 0x0100

  TIM2_ARRL=0x00;

Capture/compare enable register. The configuration of this register can select the corresponding Tim2 channel.

bit5, bit4 are configured for ch2, bit1, bit0 are configured for ch1

If OC1 is currently an output channel, then

bit1: OC1 low level is valid

bit0: OC1 signal is output to the current pin

  TIM2_CCER1=bit0|bit1; //low level,OC1

Capture/Compare Mode Register,

bit1,bit0

CC1S[1:0] is capture/compare selection

        00: CC1 channel is configured as output

bit2 reserved

bit3 output compare preload enable

    0: Disable

    1: Enable

bit6, bit5, bit4 output comparison mode

    110: PWM1 mode

Difference between PWM1 and PWM2 modes

PWM1: CNT

PWM2: CNT>CCR, CH1 is activated

TIM2_CCMR1=bit3|bit5|bit6; //MODE

Capture/compare register, this register determines the duty cycle of PWM. CCR/ARR = PWM duty cycle, for example, if it is set to 0x0060, then the duty cycle is 0x0060/0x0100=6/16

  TIM2_CCR1H=0x00;

  TIM2_CCR1L=0x60;

Interrupt enable register. If an interrupt is required, it can be set here.

bit1: CC1E capture/compare 1 interrupt enable

    0: CC1 interrupt is disabled

    1: CC1 interrupt enable

  TIM2_IER=0x00; //Update interrupt enable

Control register, bit0 controls the opening and closing of the counter.

bit0, counter enable

    0: Disable

    1: Enable

  TIM2_CR1=bit0; //enable counter

The output level of the PD4 pin is tested by a logic analyzer, and the waveform is shown below.

The source code is as follows,

//*******************************************

 1 #define bit0 0x01 

 2 #define bit1 0x02 

 3 #define bit2 0x04 

 4 #define bit3 0x08 

 5 #define bit4 0x10 

 6 #define bit5 0x20 

 7 #define bit6 0x40 

 8 #define bit7 0x80

 9 

10 void Timer2_Init(void) 

11 { 

12 CLK_ICKR|=0x01; //Turn on internal HSI 

13 while(!(CLK_ICKR&0x02));//HSI is ready 

14 CLK_SWR=0xe1; //HSI is the main clock source 

15 CLK_CKDIVR=0x00; //HSI, 8 division=16M 

16 TIM2_PSCR=0x00; //Division value=0 16M 

17 TIM2_ARRH=0x01; //Automatically reload the value 0x0100 

18 TIM2_ARRL=0x00; 

19 TIM2_CCER1=bit0|bit1; //low level,OC1

20  

21 TIM2_CCMR1=bit3|bit5|bit6; //MODE 

22 TIM2_CCR1H=0x00; 

23 TIM2_CCR1L=0x60; 

24 TIM2_IER=0x00; //Update interrupt enable 

25 

26 TIM2_CR1=bit0; //enable counter 

27 }

28 int main( void ) 

29 { 

30 Timer2_Init(); 

31 while(1){}; 

32 }