STM32 system learning - I2C (read and write EEPROM)

The I2C communication protocol (Inter-Integrated Circuit) has few pins, simple hardware implementation, strong scalability, and does not require external transceiver equipment such as USART and CAN communication protocols. It is now widely used for communication between multiple integrated circuits (ICs) within a system. 

In computer science, most complex problems can be simplified by layering. For example, the chip is divided into the core layer and on-chip peripherals; the STM32 standard library is the software layer between registers and user code. For communication protocols, we also understand them in a layered way. The most basic way is to divide them into the physical layer and the protocol layer. 

The physical layer specifies the characteristics of the mechanical and electronic functional parts of the communication system to ensure the transmission of the original data on the physical media. The protocol layer mainly specifies the communication logic and unifies the data packaging and unpacking standards of the sender and receiver. In simple terms, the physical layer specifies whether we communicate with our mouth or body, while the protocol layer specifies whether we communicate in Chinese or English. 

1. I2C physical layer 

Its physical layer has the following characteristics: 

(1) It is a bus that supports devices. "Bus" refers to the signal line shared by multiple devices. In an I2C communication bus, multiple I2C communication devices can be connected, supporting multiple communication masters and multiple communication slaves. 

(2) An I2C bus uses only two bus lines, a bidirectional serial data line (SDA) and a serial clock line (SCL). The data line is used to represent data, and the clock line is used to synchronize data transmission and reception. 

(3) Each device connected to the bus has an independent address, which the host can use to access different devices. 

(4) The bus is connected to the power supply through a pull-up resistor. When the I2C device is idle, it will output a high impedance state. When all devices are idle and output a high impedance state, the pull-up resistor pulls the bus to a high level. 

(5) When multiple hosts use the bus at the same time, arbitration is used to determine which device occupies the bus in order to prevent data conflicts. 

(6) It has three transmission modes: standard mode with a transmission rate of 100kbit/s, fast mode with a transmission rate of 400kbit/s, and high-speed mode with a transmission rate of up to 3.4Mbit/s. However, most I2C devices currently do not support high-speed mode. 

(7) The number of ICs connected to the same bus is limited by the maximum capacitance of the bus, which is 400pF.

2. Protocol Layer 

The I2C protocol defines the communication start and stop signals, data validity, response, arbitration, clock synchronization and address broadcast.

1. Basic reading and writing process 

After the start signal is generated, all slaves begin to wait for the slave address signal (SLAVE_ADDRESS) broadcast by the host. On the I2C bus, the address of each device is unique. When the address broadcast by the host is the same as the address of a device, the device is selected, and the unselected device will ignore the subsequent data signals. 

According to the I2C protocol, this slave address can be 7 bits or 10 bits. 

After the address bit, there is a transmission direction selection bit. When this bit is 0, it means that the following data transmission direction is from the host to the slave, that is, the host writes data to the slave. When this bit is 1, it is the opposite. 

After the slave receives a matching address, the host or slave will return an ACK or NACK signal. Only after receiving the ACK signal can the host continue to send or receive data. 

Writing Data 

If the configured transmission direction is "write data", that is, the first picture, after broadcasting the address and receiving the response signal, the host starts to formally transmit data (DATA) to the slave. The size of the data packet is 8 bits. After each byte of data is sent, the host must wait for the response signal (ACK) from the slave. Repeatedly, N data can be transmitted to the slave. There is no size limit for N. When the data transmission is completed, the host sends a stop transmission signal (P) to the slave, indicating that no more data will be transmitted.

Read Data 

If the configured transmission direction is "read data", that is, the second picture, after broadcasting the address and receiving the response signal, the slave starts to return data (DATA) to the host, and the data packet size is also 8 bits. After each data is sent, the slave will wait for the host's response signal (ACK). Repeating this process, it can return N data, and there is no size limit for this N. When the host wants to stop receiving data, it returns a non-response signal (NACK) to the slave, and the slave automatically stops data transmission. 

Reading and writing data 

In addition to basic reading and writing, I2C communication is more commonly used in a composite format, that is, the third figure. The transmission process has two start signals (S). Generally, in the first transmission, the host finds the slave device through SLAVE_ADDRESS and sends a piece of "data". This piece of data is usually used to represent the register or memory address inside the slave device (note the difference between it and SLAVE_ADDRESS); in the second transmission, the content of the address is read or written. In other words, the first communication is to tell the slave to read and write addresses, and the second is the actual content of reading and writing. 

The various signals included in the above communication process are decomposed as follows: 

2. Communication start and stop signals 

The start (S) and stop (P) signals are two special states. 

When the SCL line is high, the SDA line switches from high to low, which indicates the start of communication. When the SCL line is high, the SDA line switches from low to high, which indicates the end of communication. The start and stop signals are generally generated by the host. 

3. Data validity 

I2C uses the SDA signal line to transmit data and the SCL signal line for data synchronization. The SDA data line transmits one bit of data in each clock cycle of SCL. During transmission, when SCL is at a high level, the data represented by SDA is valid, that is, when SDA is at a high level at this time, it represents data "1", and when it is at a low level, it represents data "0". When SCL is at a low level, the data of SDA is invalid. Generally, at this time, SDA switches the level to prepare for the next data representation.  

4. Address and data direction 

Each device on the I2C bus has its own independent address. When the host initiates communication, it sends the device address (SLAVE_ADDRESS) through the SDA signal line to find the slave. The I2C protocol stipulates that the device address can be 7 or 10 bits. In practice, the 7-bit address is more widely used. A data bit following the device address is used to indicate the direction of data transmission. It is the data direction bit (R/W), the 8th or 11th bit. When the data direction bit is "1", it means that the host reads data from the slave. When the bit is "0", it means that the host writes data to the slave. 

5. Response 

I2C data and address transmissions are accompanied by responses. Responses include two signals: "acknowledgement (ACK)" and "non-acknowledgement (NACK)". As a data receiver, when a device (regardless of the master or slave) receives a byte of data or address transmitted by I2C, if it wants the other party to continue sending data, it needs to send an "acknowledgement (ACK)" signal to the other party, and the sender will continue to send the next data; if the receiving end wants to end the data transmission, it sends a "non-acknowledgement (NACK)" signal to the other party, and the sender will generate a stop signal after receiving the signal to end the signal transmission.

3. I2C structure and characteristics of STM32 

If we directly control the two GPIO pins of STM32, use them as SCL and SDA respectively, and control the output of the pins directly like controlling an LED light (read the SDA level when receiving data) according to the timing requirements of the above signals, we can achieve I2C communication. Similarly, if we control the pins according to the requirements of USART, we can also achieve USART communication. So as long as we comply with the protocol, it is standard communication. No matter how you implement it, whether it is a controller produced by ST or a memory produced by ATMEL, it can interact according to the communication standard. Since the CPU needs to control the pin status at each moment when directly controlling the GPIO pin level to generate the communication timing, it is called the "software simulation protocol" method. 

In contrast, there is also the "hardware protocol" method. The STM32's I2C on-chip peripheral is specifically responsible for implementing the I2C communication protocol. Once the peripheral is configured, it will automatically generate communication signals according to the protocol requirements, send and receive data, and cache them. The CPU only needs to detect the status of the peripheral and access the data register to complete data transmission and reception. This method of processing the I2C protocol by hardware peripherals reduces the CPU's work. 

1. Introduction to peripherals 

The I2C peripheral of STM32 can be used as the host and slave of communication, supporting 100Kbit/s and 400Kbit/s rates, 7-bit and 10-bit device addresses, DMA data transmission, and data verification. Its I2C peripheral also supports SMBus2.0 protocol, which is similar to I2C and is mainly used in battery management of laptop computers. 

2. Framework analysis* 

1) Communication pins 

All the hardware architecture of I2C is based on the SCL and SDA lines on the left side of the figure (the SMBA line is used for the SMBUS warning signal and is not used in I2C communication).