Storage - SDRAM

Set up SDRAM, copy the program to SDRAM, and then jump to SDRAM to continue execution

@******************************************************************************

@ File：head.s

@ Function: Set up SDRAM, copy the program to SDRAM, and then jump to SDRAM to continue execution

@******************************************************************************       

.text

.global _start

_start:

                                            @Functions disable_watch_dog, memsetup, init_nand, nand_read_ll are defined in init.c

            ldr sp, =4096 @Set up the stack 

            bl      disable_watch_dog       @关WATCH DOG

            bl memsetup @ Initialize SDRAM

            bl nand_init @Initialize NAND Flash

                                            @Copy the 1024 bytes of code starting at address 4096 in NAND Flash (compiled from main.c) to SDRAM

                                            The @nand_read_ll function requires 3 parameters:

            ldr r0, =0x30000000 @1. Target address = 0x30000000, which is the starting address of SDRAM

            mov r1, #4096 @2. Source address = 4096. When linking, the code in main.c is stored at the beginning of NAND Flash address 4096.

            mov r2, #2048 @3. Copy length = 2048 (bytes), which is enough for main.c of this experiment

            bl nand_read @Call C function nand_read

            ldr sp, =0x34000000 @Set up the stack

            ldr lr, =halt_loop @Set the return address

            ldr pc, =main @b instruction and bl instruction can only jump forward and backward within the range of 32M, so here we use the method of assigning value to pc to jump

halt_loop:

            b       halt_loop

heat.c

/* WOTCH DOG register */

#define WTCON (*(volatile unsigned long *)0x53000000)

/* SDRAM directors */

#define MEM_CTL_BASE 0x48000000

void disable_watch_dog();

void memsetup();

/*After power on, WATCH DOG is on by default, turn it off*/

void disable_watch_dog()

{

WTCON = 0;

}

/* Set 13 registers to control SDRAM */

void memsetup()

{

int i = 0;

unsigned long *p = (unsigned long *)MEM_CTL_BASE;

    /* Values ​​of 13 SDRAM registers*/

    unsigned long  const    mem_cfg_val[]={ 0x22011110,     //BWSCON

                                            0x00000700,     //BANKCON0

                                            0x00000700,     //BANKCON1

                                            0x00000700,     //BANKCON2

                                            0x00000700,     //BANKCON3  

                                            0x00000700,     //BANKCON4

                                            0x00000700,     //BANKCON5

                                            0x00018005,     //BANKCON6

                                            0x00018005,     //BANKCON7

                                            0x008C07A3,     //REFRESH

                                            0x000000B1, //BANKSIZE

                                            0x00000030,     //MRSRB6

                                            0x00000030,     //MRSRB7

                                    };

for(; i < 13; i++)

p[i] = mem_cfg_val[i];

}

nand.c

#define LARGER_NAND_PAGE

#define GSTATUS1        (*(volatile unsigned int *)0x560000B0)

#define BUSY            1

#define NAND_SECTOR_SIZE    512

#define NAND_BLOCK_MASK     (NAND_SECTOR_SIZE - 1)

#define NAND_SECTOR_SIZE_LP    2048

#define NAND_BLOCK_MASK_LP     (NAND_SECTOR_SIZE_LP - 1)

typedef unsigned int S3C24X0_REG32;

/* NAND FLASH (see S3C2410 manual chapter 6) */

typedef struct {

    S3C24X0_REG32   NFCONF;

    S3C24X0_REG32   NFCMD;

    S3C24X0_REG32   NFADDR;

    S3C24X0_REG32   NFDATA;

    S3C24X0_REG32   NFSTAT;

    S3C24X0_REG32   NFECC;

} S3C2410_NAND;

/* NAND FLASH (see S3C2440 manual chapter 6, www.100ask.net) */

typedef struct {

    S3C24X0_REG32   NFCONF;

    S3C24X0_REG32   NFCONT;

    S3C24X0_REG32   NFCMD;

    S3C24X0_REG32   NFADDR;

    S3C24X0_REG32   NFDATA;

    S3C24X0_REG32   NFMECCD0;

    S3C24X0_REG32   NFMECCD1;

    S3C24X0_REG32   NFSECCD;

    S3C24X0_REG32   NFSTAT;

    S3C24X0_REG32   NFESTAT0;

    S3C24X0_REG32   NFESTAT1;

    S3C24X0_REG32   NFMECC0;

    S3C24X0_REG32   NFMECC1;

    S3C24X0_REG32   NFSECC;

    S3C24X0_REG32   NFSBLK;

    S3C24X0_REG32   NFEBLK;

} S3C2440_NAND;

typedef struct {

    void (*nand_reset)(void);

    void (*wait_idle)(void);

    void (*nand_select_chip)(void);

    void (*nand_deselect_chip)(void);

    void (*write_cmd)(int cmd);

    void (*write_addr)(unsigned int addr);

    unsigned char (*read_data)(void);

}t_nand_chip;

static S3C2410_NAND * s3c2410nand = (S3C2410_NAND *)0x4e000000;

static S3C2440_NAND * s3c2440nand = (S3C2440_NAND *)0x4e000000;

static t_nand_chip nand_chip;

/* Function for external calls*/

void nand_init(void);

void nand_read(unsigned char *buf, unsigned long start_addr, int size);

/* The total entry for NAND Flash operations, which will call the corresponding functions of S3C2410 or S3C2440*/

static void nand_reset(void);

static void wait_idle(void);

static void nand_select_chip(void);

static void nand_deselect_chip(void);

static void write_cmd(int cmd);

static void write_addr(unsigned int addr);

static unsigned char read_data(void);

/* S3C2410 NAND Flash processing function */

static void s3c2410_nand_reset(void);

static void s3c2410_wait_idle(void);

static void s3c2410_nand_select_chip(void);

static void s3c2410_nand_deselect_chip(void);

static void s3c2410_write_cmd(int cmd);

static void s3c2410_write_addr(unsigned int addr);

static unsigned char s3c2410_read_data();

/* S3C2440 NAND Flash processing function*/

static void s3c2440_nand_reset(void);

static void s3c2440_wait_idle(void);

static void s3c2440_nand_select_chip(void);

static void s3c2440_nand_deselect_chip(void);

static void s3c2440_write_cmd(int cmd);

static void s3c2440_write_addr(unsigned int addr);

static unsigned char s3c2440_read_data(void);

/* S3C2410 NAND Flash operation function*/

/* Reset */

static void s3c2410_nand_reset(void)

{

    s3c2410_nand_select_chip();

    s3c2410_write_cmd(0xff); // reset command

    s3c2410_wait_idle();

    s3c2410_nand_deselect_chip();

}

/* Wait for NAND Flash to be ready*/

static void s3c2410_wait_idle(void)

{

    int i;

    volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFSTAT;

    while(!(*p & BUSY))

        for(i=0; i<10; i++);

}

/* Send chip select signal */

static void s3c2410_nand_select_chip(void)

{

    int i;

    s3c2410nand->NFCONF &= ~(1<<11);

    for(i=0; i<10; i++);    

}

/* Cancel chip select signal*/

static void s3c2410_nand_deselect_chip(void)

{

    s3c2410nand->NFCONF |= (1<<11);

}

/* Issue a command */

static void s3c2410_write_cmd(int cmd)

{

    volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFCMD;

    *p = cmd;

}

/* Sending address */

static void s3c2410_write_addr(unsigned int addr)

{

    int i;

    volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFADDR;

    *p = addr & 0xff;

    for(i=0; i<10; i++);

    *p = (addr >> 9) & 0xff;

    for(i=0; i<10; i++);

    *p = (addr >> 17) & 0xff;

    for(i=0; i<10; i++);

    *p = (addr >> 25) & 0xff;

    for(i=0; i<10; i++);

}

/* Read data */

static unsigned char s3c2410_read_data(void)

{

    volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFDATA;

    return *p;

}

/* S3C2440 NAND Flash operation function*/

/* Reset */

static void s3c2440_nand_reset(void)

{

    s3c2440_nand_select_chip();

    s3c2440_write_cmd(0xff); // reset command

    s3c2440_wait_idle();

    s3c2440_nand_deselect_chip();

}

/* Wait for NAND Flash to be ready*/

static void s3c2440_wait_idle(void)

{

    int i;

    volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFSTAT;

    while(!(*p & BUSY))

        for(i=0; i<10; i++);

}

/* Send chip select signal */

static void s3c2440_nand_select_chip(void)

{

    int i;

    s3c2440nand->NFCONT &= ~(1<<1);

    for(i=0; i<10; i++);    

}

/* Cancel chip select signal*/

static void s3c2440_nand_deselect_chip(void)

{

    s3c2440nand->NFCONT |= (1<<1);

}

/* Issue a command */

static void s3c2440_write_cmd(int cmd)

{

    volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFCMD;

    *p = cmd;

}

/* Sending address */

static void s3c2440_write_addr(unsigned int addr)

{

    int i;

    volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFADDR;

    *p = addr & 0xff;

    for(i=0; i<10; i++);

    *p = (addr >> 9) & 0xff;

    for(i=0; i<10; i++);

    *p = (addr >> 17) & 0xff;

    for(i=0; i<10; i++);

    *p = (addr >> 25) & 0xff;

    for(i=0; i<10; i++);

}

static void s3c2440_write_addr_lp(unsigned int addr)

{

int i;

volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFADDR;

int col, page;

col = addr & NAND_BLOCK_MASK_LP;

page = addr / NAND_SECTOR_SIZE_LP;

*p = col & 0xff; /* Column Address A0~A7 */

for(i=0; i<10; i++);

*p = (col >> 8) & 0x0f; /* Column Address A8~A11 */

for(i=0; i<10; i++);

*p = page & 0xff; /* Row Address A12~A19 */

for(i=0; i<10; i++);

*p = (page >> 8) & 0xff; /* Row Address A20~A27 */

for(i=0; i<10; i++);

*p = (page >> 16) & 0x03; /* Row Address A28~A29 */

for(i=0; i<10; i++);

}

/* Read data */

static unsigned char s3c2440_read_data(void)

{

    volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFDATA;

    return *p;

}

/* Reset NAND Flash before using it for the first time */

static void nand_reset(void)

{

    nand_chip.nand_reset();

}

static void wait_idle(void)

{

    nand_chip.wait_idle();

}

static void nand_select_chip(void)

{

    int i;

    nand_chip.nand_select_chip();

    for(i=0; i<10; i++);

}

static void nand_deselect_chip(void)

{

    nand_chip.nand_deselect_chip();

}

static void write_cmd(int cmd)

{

    nand_chip.write_cmd(cmd);

}

static void write_addr(unsigned int addr)

{

    nand_chip.write_addr(addr);

}

static unsigned char read_data(void)

{

    return nand_chip.read_data();

}

/* Initialize NAND Flash */

void nand_init(void)

{

#define TACLS   0