51 MCU Series Knowledge 3--Memory (2)

3. The lower 128 units of the internal data memory (00H~7FH)

The total capacity of the internal data memory of the 51 microcontroller is 256 bytes, and the address ranges from 00H to FFH. This 256-byte address space can be divided into a low 128-byte unit and a high 128-byte unit with different functions.

In the 256-byte internal data memory, there is also a "bit address" space (not independent). Some of the bits are in the lower 128 units, and the other part is in the upper 128 units. Therefore, there are some units in the internal data memory that can be operated on by byte or on a single bit in the unit.

The upper 128 bytes store special function registers, but there are also many empty units. These units are reserved for new models of 51 series microcontrollers. Some new models of microcontrollers have added a lot of special function registers due to the increase of internal functional devices. In order to make the software compatible with the new microcontroller, the user program should not write to the empty units. Therefore, it can be considered that the lower 128 units are the real internal data storage, so sometimes it is simply called internal "RAM".

According to its purpose, it can be divided into three areas: working register area, bit address area, and user RAM area.

① Working register area

The CPU of 51 single-chip microcomputer does not have registers like AX and BX in 8086 CPU. But this does not mean that the single-chip microcomputer does not need registers when working. Using registers is not only conducive to improving the execution speed of single-chip microcomputer, but also improves the flexibility of program compilation and simplifies program design. The registers in 51 single-chip microcomputer are not in the CPU, but appear in the form of a unit of the internal data register.

The 0~1FH area of ​​the internal RAM has four groups of working register areas, each area has 8 working registers R0~R7, and the corresponding relationship between registers and RAM unit addresses is as shown in the textbook P47.

The working register currently used by the CPU is indicated by the third and fourth bits of the program status word PSW. The correspondence between these two bits in PSW and the register used is as follows:

The CPU can select any working register area by modifying the status of RS1 and RS0 in PSW. This feature improves the speed of field protection and field recovery of 51 microcontrollers?

② Bit address space

The 20H~2FH units in the internal RAM of the 51 single-chip microcomputer and the SFRs with addresses that are multiples of 8 in the special function registers can be bit-addressed, and they constitute the bit storage of the 51 single-chip microcomputer. This bit processing capability is an important feature of the 51 single-chip microcomputer. These units have both a byte address (8 bits as a whole address) and a bit address for each bit. The bit addressing of these units can be found in the textbook P49 and P50. This function of operating bits (setting, clearing, inverting, testing) provides a simple and clear method to directly convert logic (combinatorial logic) into software. Complex combinational logic functions can be realized without excessive data transmission, byte masking and test branch trees.

③ User RAM area

The remaining 80 units have no special provisions and are RAM areas for users to use freely. Their addresses are 30H to 70FH. In general applications, data buffers and stacks are often opened in this area. The top of the stack is pointed out by the stack pointer SP. When pushing the stack, the stack pointer (SP) of MCS-51 first adds "1", and then the data is pushed into the stack (written into the stack area pointed out by SP); when popping the stack, the data is first popped out (the content of the unit pointed out by SP is read out), and then SP is reduced by "1". Because (SP) is 07H after reset, this means that the stack area is set in the RAM area starting at 08H, and 08H to 1FH is the working register area. Generally, the stack area should be specifically set by initializing SP, such as 6FH → SP, then the stack is set in the area starting at 70H.

Other areas can be used as data buffers to store input data or calculation results.

3. The upper 128 cells of the internal data memory

The CPU registers, I/O port registers, timers, serial ports, interrupts and other control registers and status registers inside the 51 MCU are all special function registers (SFRs). There are 21 basic SFRs in the 51 MCU. The 21 SFRs are discretely separated and the addresses are not continuous.

The relationship between these 21 SFRs and various control functions is as follows (of course there are overlaps):

l CPU: A, B, PSW, PPH, DPL (compose DPTR), SP;

l Timer/Counter: TH0, TL0 (compose T0), TH1, TL1 (compose T1) TM0D, TCON;

l Interrupt system: IE, IP;

l Parallel port: PO, P1, P2, P3;

l Serial port: SCON, PCON, SBUF.

Note: (1) There is another register inside the microcontroller, the program counter PC. Although its function is also very special (storing the address of the next instruction to be executed), it is different from the register mentioned here. PC has no address and is physically independent. Therefore, PC is not listed in SFR.

      ⑵The bit space overlaps with the internal RAM and SFR, and each unprocessed bit also has a bit address, which is similar in form to the unit address space (for example, if there is unit 08, there is also bit 08H). Therefore, it depends on the nature of the instruction to determine whether the address is a unit address or a bit address.

      If it is a byte operation instruction, such as "MOVA, 08H", 08H is the unit address

      If it is a bit operation instruction, such as "MOVC, 08H", then 08H is the bit address

FFH

80H

7FH bit search address 00H～7FH

30 hours except for actual work

2FH registers four areas, the number and

20H Working register four area In addition to the number of bit marks, more

1FH R0～R7 The remaining units can be used as data

18H Data buffer or stack

17H

10H

0FH

08H

07H

00H

Data storage

FFFFH

FFH                            FFH          FFH

80H 80H

7FH 7FH 80H

00H 0000H 00H

  51 Series 52 Series

4. External data storage

The data memory of the 51 MCU is physically and technically divided into two independent address spaces: an internal and an external data storage space, each of which is addressed separately. The MOV instruction is used to access the internal data memory; the MOVX instruction is used to access the external data memory.

The 52 series microcontroller has 256 bytes of RAM and 128 bytes of SFR. The upper 128 bytes of RAM overlap with the address of SFR, but since the access instructions are different, it does not cause confusion. The off-chip RAM generally uses 16-bit addressing.

The lowest 128 addresses of the external RAM overlap with the addresses of the on-chip data memory. At the same time, the 51 MCU uniformly addresses the external RAM and I/O interface. If you expand the external RAM and I/O interface at the same time, you should pay attention to the address allocation problem. That is, when the user designs the application system, all peripheral interface addresses occupy the address unit of the external RAM. The CPU uses the same instructions for external RAM and I/O operations.