Expert summary! AVR microcontroller study notes

The following is my learning experience when learning AVR microcontrollers. I share it with everyone so that we can learn together.

1. AVR microcontrollers use RISC architecture , while 8051 microcontrollers use CISC architecture. The former is 2 to 4 times faster than the latter and uses pipeline operation instructions.

2. AVR microcontrollers have 32 general registers (addresses in RAM start from $0000 to $001F), of which 6 (the last 6) are combined into three 16-bit X, Y, and Z registers to store address pointers. The Z register can also address program memory.

3. Harvard architecture, 131 machine instructions

4. Delayed startup function

5. Built-in RC oscillator, can provide 1/2/4/8MHZ working clock

6. FLASH+EEPROM+SRAM+SPI+USART+TWI+PWM+RTC+10-bit ADC+analog comparator+JTAG

7. The stack pointer grows downwards, and the 51 MCU grows upwards

8. The program memory is accessed by word, and erased and written in pages.

9. During reset, all I/O ports are in input state without pull-up resistor (high impedance)

10. There is no interrupt priority control register. The priority is determined by the address of the interrupt vector table (the lower the address, the higher the priority)

11. PORTB |= (1<<2) D2 is set to 1, PORTB&= ~ (1<<6) D6 is cleared

12. FLASH is divided into two sections: Boot Program Section + Application Program Section. SPM instructions can be used in BPS to implement IAP function

13. The interrupt vector table is located at the front of the FLASH program memory

14. The I/O space is a continuous 64 I/O register space, and the mapping address in the data memory space is $0020~$005F. There are two ways to access the I/O register: IN, OUT instructions + SRAM access instructions

15. A separate AVcc is used to provide AREF for the ADC of PORTA

16. The 13-bit program counter PC just meets the 16KB addressing requirement.

17. AVR requires 2 clock cycles to access the on-chip SRAM

18.             

19. Status register SREG:

           I: Global interrupt enable bit. When set to 1, the CPU can respond to interrupts; when cleared to 0, the CPU is prohibited from responding to interrupts. When cleared to 0, the value of the individual interrupt trigger control remains unchanged. After the interrupt is responded, I is cleared to 0 by hardware (manually set to 1 to achieve interrupt nesting), and RETI is set to 1 to respond to other interrupts

           T: Bit copy storage. BLD, BST. You can copy any bit in the general register group to T, and vice versa.

           H: Half carry flag. Used for BCD calculation

           S: Sign flag. S=N⊕V. Regardless of overflow or not (the representation of N is incorrect after overflow!), S always correctly represents the sign of the calculation result.

           V: 2's complement overflow flag. When overflow occurs, N is negated to obtain the true result sign.

           N: Negative number flag. Directly taken from the highest bit of the calculation result

           Z: Zero value flag. If the operation result is 0, it is set to 1.

           C: Carry/borrow flag.

20. MCUCSR can check the reset reason

21. Power-off detection (BOD) reset

22. A JMP or RJMP instruction is stored in $0000H of FLASH, which is used to jump to the formal code entry. $0002H~0028H (for interrupt vectors of one word, if the interrupt vector is two words, $0002H~0050H) stores the interrupt vector table, 20 interrupt ports

23. Hardware development tools: software simulation emulator, real-time on-board emulator (ICE), real-time on-chip emulator (JTAG)

24. Each group of I/O ports is configured with three registers to represent their status: direction control register DDRx (Data Direction Register), data register PORTn, and input pin register PINx.

25. DDRx = 1, I/O port is in push-pull output mode, PORTn is 1 to output 20mA current, 0 to absorb 20mA current. DDRx = 0, I/O port is in input mode, read the level in PINx to DB (PORTn is used to set whether to use internal pull-up resistor, 1 is used, 0 is not used) There is a PUD in SFIOR, PUD = 1 all I/O pull-up resistors are invalid, PUD = 0, pull-up depends on the setting of PORTn

26. When using the I/O port, you must configure the I/O port first. First configure DDRx to determine whether the I/O port is input or output. According to the actual situation, you need to configure whether to pull up or pull down when input (pull up means the default input is high level, pull down means the default input is low level)

27. When using I/O port input mode, the value of PINx should be read

28. Output port operation:

PORTA |= (1 <

PORTA &= ~(1<< PORTAx) // Position low

PORTA ^= (1 <

Input port operation:

PINA & (1<< PORTAx) // bit read

29. There are three external interrupts (INT0, INT1, INT2), of which INT2 only supports edge triggering

30. When the interrupt condition is met, the AVR hardware automatically sets the corresponding interrupt flag to 1 and clears it automatically by the hardware (this function is only available for some interrupts, and can also be cleared manually by software by writing 1). The hardware also automatically clears the I flag at the same time (interrupt nesting is not possible by default, SEI sets I to 1 to enable interrupt nesting)

31. After exiting the interrupt, the AVR must execute at least one more instruction before responding to other suspended interrupts.

32. Interrupt response requires at least 4 CKs to start running the jump instruction in the interrupt vector table (clear I, clear interrupt flag, push PC, and send interrupt vector to PC). As for actually starting to run the user's code, at least 6~7 CKs are required. Interrupt return RETI also requires 4 CKs (pop PC, set I in SREG to 1)

33. Before enabling the interrupt enable bit, it is best to clear the interrupt flag bit of the corresponding interrupt source to prevent an "extra" interrupt from being generated immediately when enabling it.

34. INT0 and INT1 support four types of interrupt triggers: rising edge, falling edge, any level change, and low level (without interrupt flag, low level does not affect the values ​​of INTF0 and INTF1 (remains 0)). INT2 only supports asynchronous rising edge and falling edge triggers (often used to wake up the MCU)

35. Interrupt initialization steps: configure the interrupt trigger type (MCUCR, MCUCSR), enable the corresponding interrupt (GICR), clear the corresponding interrupt flag (GIFR), and enable global interrupt (asm ("SEI")). Interrupt writing in AVR STUDIO6: SIGNAL (xx) {} (x is the interrupt vector number) or ISR (xx) {}

36. T/C0 and T/C2 can generate PWM, frequency generator, external event counter (only T/C0), 10-bit clock prescaler, overflow and compare match interrupt source, allowing 32.768kHz crystal to be used as an independent counting clock source (only T/C2)

37. The clock source is similar to that of the 51 MCU: (CS[2:0] has eight options), stop counting, rising edge or falling edge, 10-bit prescaler (1/1, 1/8, 1/64, 1/256, 1/1024)

38. The TCNT0 (8-bit) register is used to store the count value. If the value is written during the counter operation, the comparison match will be blocked in the next timing clock cycle (a match operation between TCNT0 and OCR0 will be lost)

39. The data in OCR0 will be compared with the value in TCNT0. If they match, a comparison match interrupt request will be generated or the output logic level of OC0 will be changed.

40. OCIE0 (OutputCompare Interrupt Enable) and TOIE (Timer Overflow Interrupt Enable) in TIMSK are the compare match interrupt enable flag and overflow interrupt enable flag respectively. When I is set, the corresponding interrupt can be triggered when the conditions are met.

41. OCF0 (OutputCompare Flag) and TOV0 (Timer Overflow) in TIFR are the compare match flag and timer overflow flag respectively.

42. WGM[1:0] in TCCR determines the four working modes of T/C0: normal mode, timer cleared to 0 when compare match, and two PWM modes. The function of COM[1:0] compare match output mode depends on the working mode of T/C0. Normal mode (WGM[1:0]=0): Counting to 0xFF will generate an overflow interrupt, and TOV0 is set to 1. Compare match clear counter CTC mode (WGM[1:0]=2): f=f(IO)/(2N(1+OCR0)), TCNT0 and OCR0 match, after the match, TCNT0 is cleared to 0 and counts again, and OCF0 is set to 1 at the same time, which is convenient for generating interrupts. By changing the value of OCR0 in the interrupt, variable high and low level signals can be output in OC0. Fast PWM mode (WGM[1:0]=3): f=f(IO)/(256N), TCNT0 counts from 0 to 0xFF, and then restarts counting. If it matches OCR0, OC0 is set or cleared according to the setting value in COM[1:0] to output PWM waveform. Phase-adjustable PWM mode (WGM[1:0]=1): bidirectional counter, so the maximum PWM frequency is half slower than that of fast PWM mode.

43. The frequency division coefficient of T2 timer is different from that of T0, please pay attention to the difference

44. When reading data, the T1 timer reads the lower eight bits first, then the upper eight bits. When writing data, it writes the upper eight bits first, then the lower eight bits. This is like pushing the high bits onto the stack.

45. Since T1 can modify the upper limit value (TOP) of the counter, it can generate a PWM waveform with variable frequency, while T0/T2 timers cannot do this.

46. ​​The working mode of T1 is determined by WGM1[3:0]. It can be seen that T1 has 16 working modes. Normal mode (WGM1[3:0]=0). CTC mode (GWM1[3:0]=4 or 12). Fast PWM mode (GWM1[3:0]=5,6,7,14,15) has two simultaneous outputs, OC1A, OC1B

47. T1 input capture function: The trigger signal is input by ICP1 or analog comparator AC0. When triggered, the value of TCNT1 is written to ICR1 to set ICF1. In addition, ICNC (Input Capture NoiseCanceler) is a noise suppression function. The implementation principle is to delay 4 CK detection level changes. If 4 consecutive CKs remain unchanged, it is considered a real trigger. ICES (Input Capture Edge Select) is the selection of the trigger edge, 0 is the falling edge, 1 is the rising edge

48. Analog comparator (positive AIN0 and negative AIN1), ACME (Analog Comparator Multiplexer Enable) in SFIOR (Special Funciton IO Register) analog comparator multiplexer enable, set to 1 and ADC disabled, the negative pole of the comparator is connected to the multiplexer of the ADC. Set to 0, the negative pole of the comparator is connected to AIN1. ACSR (Analog Comparator Control and Status Register) analog comparator control and status register. When ACD (Analog Control Disable) is set to 1, the switch of the analog comparator is cut off. When changing the settings, ACIE should be disabled first to prohibit the generation of analog comparator interrupts. ACO (Analog Comparator Output) analog comparator output. ACIS[1:0] (Analog Comparator Interrupt Select) analog comparator interrupt mode selection

49. AVCC is the independent power supply of ADC module. The reference power supply can be selected from on-chip 2.56V, AVCC or external reference power supply

50. ADMUX (ADC multiplexing selection register), ADLAR (ADC LeftAdjust Result) result is left-aligned. ADCSRA (ADC control and status register A), ADEN, ADC enable bit. ADSC (ADC Start Conversion) start conversion bit. ADATE (ADC Auto Trigger Enable) automatically triggers the start of conversion, and the signal source is determined by the ADTS bit of SFIOR. ADPS[2:0] pre-scaling selection bit

51. If AVREF is connected to an external power supply, the internal reference power supply cannot be used.

52. After the ADC module enables ADATE (automatically trigger conversion), the overflow interrupt of T0 is used to trigger the start of conversion. The interrupt enable bit of T0 (TOIE0) must be turned on, otherwise the conversion cannot be triggered.

53. A normal ADC conversion process requires 13 sampling clocks. Assuming that the ADC sampling clock frequency is 200kHZ, the highest sampling frequency is 200kHZ/13=15.384kHZ. Therefore, according to Shannon's theorem, the highest frequency of the measured signal is 7.7kHZ.

54. Universal Synchronous and Asynchronous Serial Receiver and Transmitter supports four working modes: normal asynchronous mode, double speed asynchronous mode, master synchronous mode and slave synchronous mode. The UMSEL (U Mode Select) bit in UCSRC is used to select synchronous or asynchronous mode. U2X in UCSRA is used to control whether to use double speed mode.

55. Baud rate calculation formula: BAUD=fosc/(16(UBRR+1)).

56. When UDRE (U Data Register Empty) in UCSRA is set to 1 (the data register is empty), UDR can be written. Once written, the hardware automatically sends the content to TXD for serial shifting out. Both RXD and TXD can generate corresponding interrupts, and the flag is automatically cleared to 0 after entering the interrupt.

57. Since the physical addresses of UBRRH (U Baud Rate Register) and UCSRC are the same, only the highest bit URSEL is different, and the objects of write and read operations are different. When URSEL is 0, the object is UBRRH; when URSEL is 1, the object is UCSRC. (When reading UCSRC, it is necessary to read it twice in succession to get the result. The first read is the value of UBRRH)

58. USART initialization includes: setting the baud rate, enabling the receiver and transmitter, and setting the frame format

 Data transmission: while(!(UCSRA& (1 << UDRE))); UDR = data; UDRE is automatically cleared by hardware after the value is written to UDR. If UDR is not assigned a value in the UDR empty interrupt, UDRE is not cleared, and the interrupt will be triggered again after exiting the interrupt. However, the TXC interrupt can automatically clear the TXC flag by hardware.

        Data reception: while(!(UCSRA & (1 << RXC)));data = UDR;RXC is automatically cleared by hardware after the UDR data is read out, so UDR must be read during RXC interrupt to clear RXC. Or manually clear RXC

       The TXD and RXD functions are turned on and off by the settings of TXEN and RXEN.

59. If FE, PE, and DOR in UCSRA need to be read out for error detection in the RXC interrupt, then UCSRA must be read first and then UDR.

60. Serial Peripheral Interface (SPI. Proposed by Freescale), Two-wire Serial Interface (TWI). SPI generally has four signal lines: MOSI, MISO, SCLK, /SS. You can imagine that the host and the slave are connected from MOSI to MISO to form a ring (essentially serial shift). When all the data are exchanged, the host pulls up /SS to stop SPI transmission. This is why SPI is faster than TWI (I2C): because the data is full-duplex and the data goes through different channels.

61. SPI has four working modes, depending on two parameters: the polarity of the synchronous clock (Clock Polariy) and the phase of the synchronous clock (Clock Phase).

62. The maximum speed of SPI master mode is (CK/2), and the maximum speed of slave mode is (CKI/4)

63. Data register SPDR. When reading SPDR, the buffer register content is read; when writing SPDR, it is written to the shift register. Once the data is written to SPDR, the hardware automatically transmits an SPI communication, and if the interrupt is allowed, it enters the SPI interrupt.

64. The SPI rate is generally 1MHZ, and can reach up to 10MHZ

65. When TWI works in slave mode, the CPU frequency fcpuclock must be greater than 16 times the TWI clock line SCL frequency. SCL frequency: (In host mode, TWBR should be greater than 10. Another point that needs special attention: It does not refer to 4 TWPS, but should be replaced by 1, 4, 16, 64 in the table according to the frequency division table)

66. TWINT interrupt flag. When it is set, the clock line SCL is pulled low, and when the interrupt vector is executed, the flag will not be cleared to 0 and can only be cleared to 0 by manual software.

67. If TWINT is set, it means that data is being transmitted. If TWDR is written at this time, TWWC (write conflict) will be set. That is to say, when TWINT is set, TWDR should remain stable, which is consistent with the I2C protocol.

68. The upper 7 bits of TWAR (address register) are used to store its own address, and the last bit TWGCE (TWI General Call Recognition Enable) is the address match success enable bit. If the address match is successful, a TWI interrupt will be generated.

69. In the TWI register setting of I2C, you cannot use | to assign values, you must assign values ​​as a whole

70. CKOPT is set to 1 when the system frequency is high or strong anti-interference ability is required. If the system frequency is low, set it to 0 to reduce current loss.

71. When performing a read operation on the on-chip EEPROM, the CPU stops running for 4 clock cycles. When performing a write operation, the CPU stops running for 2 clock cycles.