55.SPI interface principle and configuration

This experiment uses the W25Q64 chip

    W25Q64 is a large-capacity SPI FLASH product launched by Winbond, with a capacity of 64Mb. The 25Q series devices far exceed ordinary serial flash devices in terms of flexibility and performance. W25Q64 divides the 8M-byte capacity into 128 blocks, each block is 64K bytes, each block is divided into 16 sectors, each sector is 4K bytes. The minimum erase unit of W25Q64 is one sector, which means that 4K bytes must be erased each time. Therefore, it is necessary to open up a cache area of ​​at least 4K for W25Q64, so the chip must have more than 4K SRAM to operate well. 

    The W25Q64 has an erase and write cycle of up to 10W times and can store data for up to 20 years. It supports a voltage of 2.7~3.6V, standard SPI, and dual-output/quad-output SPI, with a maximum SPI clock of up to 80Mhz.

1. SPI interface principle

(I. Overview

High-speed, full-duplex, synchronous communications bus.

Full-duplex: can send and receive at the same time, requires 2 pins

Synchronization: Requires clock pin

Chip select pin: It is convenient to connect multiple devices to one SPI interface.

Four pins total.

(II) Simple diagram of SPI internal structure

MISO: input when acting as a master, output when acting as a slave

MOSI: output when acting as a master, input when acting as a slave

The host and the slave both have a shift register. Under the control of the same clock, the highest bit of the host is moved to the highest bit of the slave, and the highest bit of the slave is moved forward one bit to the lowest bit of the host. Under the control of one clock, the host and the slave exchange one bit, then under the control of 8 clocks, 8 bits are exchanged. The final result is that the data of the two shift registers are completely exchanged.

Under the control of 8 clocks, the two bytes of the host and the slave are exchanged, that is, when the host sends a byte of 8 bits to the slave, the slave also sends back 8 bits, that is, one byte, to the host.

(III) SPI interface block diagram

The left part above shows how data is transmitted under clock control. The right side is the control unit, which also includes the baud rate generator on the lower left.

(IV) Summary of SPI working principle

5. Characteristics of SPI

(vi) Management from the selection (NSS) foot

First of all, the two SPI communications have two data lines, a clock line, and a chip select line. Only when the chip select is pulled low can the SPI chip work. The chip select pin can be the chip select pin specified by SPI, and you can also select any IO port as the chip select pin through software. The advantage of this is: for example, if multiple devices are hung on an SPI interface, such as 4 devices, the second one uses PA2, the third one uses PA3, and the fourth one uses PA4 as the chip select. When we communicate with the second device, we only need to select the second chip select, such as pulling it low, and the chip selects of other devices are pulled high. In this way, an SPI interface can connect to multiple SPI devices. This method is used on the battleship development board.

7. Phase and polarity of clock signals

The phase and polarity of the clock signal are determined by the CPOL and CPHA bits in the CR register.

CPOL: Clock polarity, set the idle state level of the clock when there is no data transmission. CPOL is set to 0, the SCK pin is low level when idle, CPOL is set to 1, and the SCK pin remains high level when idle.

CPHA: Clock Phase Set the clock signal at which edge the data is collected

When CPHA=1: on the second edge of the clock signal

      CPOL=1, CPHA=1, CPOL=1 means that the clock signal is at a high level when there is no data transmission, i.e. when it is idle. If CPHA=1, data is collected at the second edge of the clock signal, i.e., the rising edge.

      CPOL= 0, CPHA=1, CPOL=0 means the clock signal is at a low level when there is no data transmission, i.e. when it is idle. If CPHA=1, data is collected at the second edge of the clock signal, i.e. the falling edge.

When CPHA=0: on the first edge of the clock signal

       CPOL=1, CPHA=0, CPOL=1 means that the clock signal is at a high level when there is no data transmission, i.e. when it is idle. If CPHA=1, data is collected at the first edge of the clock signal, i.e., the falling edge.

      CPOL= 0, CPHA=0, CPOL=0 means that the clock signal is at a low level when there is no data transmission, i.e. when it is idle. If CPHA=1, data is collected at the first edge of the clock signal, i.e., the rising edge.

Why do we need to configure these two parameters?

Because the clock phase and polarity of the slave of the SPI peripheral are strictly required, we need to configure the phase and polarity of the master according to the clock phase and polarity of the selected peripheral. It must match the slave.

(VIII) Data frame format and status flags

Data frame format: Depending on the setting of the LSBFIRST bit in the CR1 register, the data can be MSB first or LSB first.

                    Each data frame can be 8 bits or 16 bits depending on the DEF bit of the CR1 register.

(IX) SPI interrupt

(10) SPI pin configuration (3 SPI)

Pin operating mode settings

The pins must be configured according to this table.

2. SPI register library function configuration

1. Commonly used registers

(II) SPI related library functions

The SPI interface of STM32 can be configured to support SPI protocol or I2S audio protocol. The default mode is SPI, which can be switched to I2S mode by software.

Commonly used functions:

1. void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); //SPI initialization

2. void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); //SPI enable

3. void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); // Enable interrupt

4. void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); //Transfer data via DMA

5. void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); //Send data

6. uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); //Receive data

7. void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); //Set the data to 8 bits or 16 bits

8. Several other state functions

void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); //SPI initialization

There are many structure member variables. Here we pick out several important member variables to explain:

The first parameter SPI_Direction is used to set the SPI communication mode. You can choose half-duplex, full-duplex, and serial transmission and serial reception. Here we choose the full-duplex mode SPI_Direction_2Lines_FullDuplex.

The second parameter SPI_Mode is used to set the master-slave mode of SPI. Here we set it to the master mode SPI_Mode_Master. Of course, you can also choose the slave mode SPI_Mode_Slave if necessary.

The third parameter SPI_DataSiz is an 8-bit or 16-bit frame format selection item. Here we are transmitting 8 bits, so select SPI_DataSize_8b.

The fourth parameter SPI_CPOL is used to set the clock polarity. We set the idle state of the serial synchronous clock to a high level so we select SPI_CPOL_High.

The fifth parameter SPI_CPHA is used to set the clock phase, that is, to select the number of transition edges (rising or falling) of the serial synchronous clock at which the data is sampled. It can be the first or second edge. Here we choose the second transition edge, so select SPI_CPHA_2Edge

The sixth parameter SPI_NSS sets whether the NSS signal is controlled by hardware (NSS pin) or software. Here we use software control

To control the NSS key instead of hardware automatic control, select SPI_NSS_Soft.

The seventh parameter SPI_BaudRatePrescaler is very important. It is used to set the SPI baud rate prescaler value, which determines the SPI timing.

Clock parameters, no channel division 256 frequency division 8 optional values, we choose 256 frequency division value during initialization

SPI_BaudRatePrescaler_256, the transmission speed is 36M/256=140.625KHz.

The eighth parameter SPI_FirstBit sets the data transmission order to be MSB first or LSB first. Here we choose

SPI_FirstBit_MSB High bit first.

The ninth parameter SPI_CRCPolynomial is used to set the CRC check polynomial to improve communication reliability. It can be greater than 1.

After setting the above 9 parameters, we can initialize the SPI peripheral.

The sample format of initialization is:

SPI_InitTypeDef SPI_InitStructure;

SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; //Two-line bidirectional full-duplex

SPI_InitStructure.SPI_Mode = SPI_Mode_Master; //Master SPI

SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; //SPI sends and receives 8-bit frame structure

SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; //The idle state of the serial synchronous clock is high 

371

SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; //The second transition edge data is sampled

SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; //NSS signal is controlled by software

SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256; //Prescaler 256

SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; //Data transmission starts from the MSB bit

SPI_InitStructure.SPI_CRCPolynomial = 7; // CRC value calculation polynomial

SPI_Init(SPI2, &SPI_InitStructure); //Initialize the peripheral SPIx register according to the specified parameters

(III) Program configuration steps

3. W25Qxx Configuration Explanation

1. Circuit diagram

The PB12 chip is selected

W25Q64 is a large-capacity SPI FLASH product launched by Winbond. The capacity of W25Q64 is 64Mb. The series also includes W25Q80/16/32, etc. The capacity of W25Q64 selected by ALIENTEK is 64Mb, which is 8M bytes. (1M=1024K)

    W25Q64 divides 8M capacity into 128 blocks, each block is 64K bytes, each block is divided into 16 sectors, each sector is 4K bytes. The minimum erase unit of W25Q64 is one sector, which means 4K bytes must be erased each time. In this way, we need to open up a cache area of ​​at least 4K for W25Q64, which has a relatively high requirement for SRAM. The chip must have more than 4K SRAM to operate well.

    The erase and write cycles of W25Q64 are up to 10W times, with a data retention period of 20 years and a supported voltage of 2.7~3.6V. W25Q64 supports standard SPI and dual-output/quad-output SPI. The maximum SPI clock can reach 80Mhz (equivalent to 160Mhz for dual output and 320Mhz for quad output). For more information about W25Q64, please refer to the DATASHEET of W25Q64.

   Before writing data to an address, all the data in the sector must be read out and saved in the cache, then the sector must be erased, the data to be written must be modified in the cache, and then the data in the entire cache must be rewritten to the sector that was just erased.