Msp430f5419/38 study notes USCI: UART mode

   The msp430f541x and msp430f543x have up to 4 universal serial communication interface (USCI) modules, supporting multiple serial communication modes. Different USCI modules support different modes.

  USCI_Ax module supports:

• UART mode;

• Pulse shaping for IrDA communications;

• Automatic baud rate detection for LIN communication;

• SPI mode;

  USCI_Bx module supports:

• IIC mode;

• SPI mode;

UART Mode:

    In asynchronous mode, the USCI_Ax module connects the chip to the external system through two external pins UCAxRXD and UCAxTXD.

When the bit is cleared to 0, UART mode is selected.

  UART module features include:

• 7 or 8-bit data with odd, even or no parity;

• Independent transmit and receive shift registers;

• Independent transmit and receive buffer registers;

• Independent interrupt capability for sending and receiving;

• Data transmission and reception with least significant bit first or most significant bit first;

• Built-in idle line and address bit communication protocols for multiprocessor systems;

• Receiver start edge detection for automatic wake-up from LPMx mode;

• Baud rate is programmable and supports fractional baud rate modulation;

• Status flags for error detection and suppression;

• Status flags for address detection;

1. USCI initialization and reset

   The USCI can be reset by PUC or by setting UCSWRST. After PUC, the UCSWRST bit is automatically set, which keeps the USCI in reset state. Setting the UCSWRST bit will reset the UCRXIE, UCTXIE, UCRXIFG, UCRXERR, UCBRK, UCPE, UCOE, UCFE, UCSTOE and UCBTOE bits, and set the UCTXIFG bit. Clearing UCSWRST will release the USCI and put it into operation. The following procedure is recommended for initialization or reconfiguration:

1. Set UCSWRST (BIS.B #UCSWRST, &UCAxCTL1);

2.2 Set UCSWRST = 1 to initialize all USCI registers (including UCAxCTL1);

3. Configure ports;

4. Software clears UCSWRST (BIC.B #UCSWRST, &UCAxCTL1);

5. Enable interrupts via UCRXIE and/or UCTXIE (optional);

Example: The serial port assistant returns whatever it sends.

#include "msp430x54x.h"

// ACLK = REFO = 32768Hz, MCLK = SMCLK = default DCO/2 = 1048576Hz

// P3.4，5——USCI_A0 TXD/RXD；P9.4,5——USCI_A2 TXD/RXD；P10.4,5——USCI_A3 TXD/RXD；

void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

  P5SEL = 0xc0;                             // P5.6,7 = USCI_A1 TXD/RXD
  UCA1CTL1 |= UCSWRST;                      // **Put state machine in reset**
  UCA1CTL1 |= UCSSEL_2;                     // SMCLK
  UCA1BR0 = 9;                              // 1MHz 115200 (see User's Guide)
  UCA1BR1 = 0;                              // 1MHz 115200
  UCA1MCTL |= UCBRS_1 + UCBRF_0;            // Modulation UCBRSx=1, UCBRFx=0
  UCA1CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
  UCA1IE |= UCRXIE;                         // Enable USCI_A1 RX interrupt

  __bis_SR_register(LPM0_bits + GIE);       // Enter LPM0, interrupts enabled
}

// Echo back RXed character, confirm TX buffer is ready first, confirm the send buffer is ready before sending data

#pragma vector=USCI_A1_VECTOR
__interrupt void USCI_A1_ISR(void)
{
  switch(__even_in_range(UCA1IV,4))
  {
  case 0:break;                             // Vector 0 - no interrupt
  case 2:                                   // Vector 2 - RXIFG
   while (!(UCA1IFG&UCTXIFG));             // USCI_A1 TX buffer ready?
    UCA1TXBUF = UCA1RXBUF;                  // TX -> RXed character
    break;
  case 4:break;                             // Vector 4 - TXIFG
  default: break;
  }
}

// UCTXIFG=0x02, UCA1IFG&UCTXIFG, when the UCTXIFG bit of UCA1IFG is 1, it means that UCA1TXBUF is empty, and the while loop is jumped out; when the UCTXIFG bit is 0, UCA1TXBUF is not empty, and the loop is stopped. 

2. USCI Interruption

    USCI has only one interrupt vector shared by both sending and receiving. USCI_Ax and USC_Bx do not share an interrupt vector.

  2.1 USCI Send Interrupt Operation

    The transmitter sets the UCTXIFG interrupt flag, which indicates that the UCAxTXBUF is ready to receive another character (i.e., UCAxTXBUF is empty). If UCTXIE and GIE are also set, an interrupt request will be generated. If a character is written, UCAxTXBUF and UCTXIFG are automatically reset without software reset. After PUC or when UCSWRST = 1, UCTXIFG is set and UCTXIE is reset.

  2.2 USCI Receive Interrupt Operation

    Each time a character is received and loaded into UCAxRXBUF, the UCRXIFG interrupt flag is set and an interrupt request is generated if UCTXIE and GIE are also set. UCRXIFG and UCRXIE can be reset by the system reset PUC signal or UCSWRST = 1. UCRXIFG is automatically reset when UCAxRXBUF is read. 

  2.3 UCAxIV, Interrupt Vector Generator

     The USCI interrupt flags have a certain priority and are combined to use an interrupt vector. The interrupt vector register UCAxIV is used to determine the flag that generates the interrupt. The enabled interrupt with the highest priority generates a value in the UCAxIV register, which can be added to the program counter to automatically jump to the corresponding software subroutine. Disabling interrupts does not affect the value of UCAxIV. 

     Any access to the UCAxIV register, read or write, will automatically reset the pending highest priority interrupt flag. If another interrupt flag is set, another interrupt will be generated immediately after the first interrupt has been serviced.  

3. Register

    3.1

     This register mainly defines the character format of data communication. The character format of UART includes a start bit, 7 or 8 data bits, an odd/even/non-parity check bit, address bit (address bit mode), and 1 or 2 stop bits. The UCMSB bit controls the transmission direction and selects low or high bit first. The typical choice for UART communication is low bit first.

     All bits after PUC are 0, which means character length is 8, 1 stop bit, no parity check, low bit first, UART mode.

   UCMODEx Bits2_1位：

   When two chips communicate asynchronously, the multiprocessor format is not required for the protocol. When three or more chips communicate, USCI
supports the line idle and address bit multiprocessor communication format.

    3.11 Line Idle Multiprocessor Mode (to be continued)

    3.12 Address Bit Multiprocessor Mode (to be continued)

    3.13 Automatic Baud Rate Detection (to be continued)

  3.2

    This register is mainly used to configure USCI. After PUC, the clock selects the external clock, so in addition to setting the UCSWRST bit during initialization, the clock source must also be configured. The rest are left as default.

4. Using USCI module in low power UART mode

    The USCI module provides automatic clock activation in low power mode. When the USCI clock source is inactive because the device is in low power mode, the USCI module activates the clock source when needed, regardless of the setting of the clock source control bit, and the clock remains active until the USCI module returns to the idle state. After the USCI module returns to the idle state, the setting of the clock source control bit is reversed.

eg.
void InitUARTA1(void)
{
  UCA1CTL1 |= UCSWRST;// After PUC, the UCSWRST bit is automatically set, which keeps the USCI in reset state
  UCA1CTL0 = 0x00;                         
  UCA1CTL1 |= UCSSEL_2; // SMCLK
  UCA1BR0 = 216; // 24MHz 115200
  UCA1BR1 = 0; // 24MHz 115200
  UCA1MCTL = UCBRS_2 + UCBRF_0; // 0x04+0x00
  P5SEL = 0xC0; // P5.6/7 = USCI_A0 TXD/RXD
  UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**,。 Clearing UCSWRST will release USCI, UCA1IE |= UCRXIE; // Enable USCI_A1 RX interrupt
}
#pragma vector = USCI_A1_VECTOR
__interrupt void USCI_A1_ISR(void)
{
  switch (__even_in_range(UCA1IV,4))
  {
  case 0:break;                             
  case 2:
   g_uartBufA[g_bufALen] = UCA1RXBUF;
   if (g_uartBufA[g_bufALen]==0xFF)
   {
    }
   if (g_uartBufA[g_bufALen++]==0xFD) //Judge whether the command frame sent by the PC is completed
   {
     g_bufALen=0;
     g_uartReceive = 1;// Set
   }
  break;
  case 4:break; // Vector 4 - TXIFG
  default: break;
  }
}
void USciSend()
{
  unsigned char i;
  for (i = 0; i < g_bufALen; i++)
  {
    while (!(UCA1IFG & UCTXIFG));
    UCA1TXBUF = g_uartBufA[uartBuf1];
  }
} // UCA1MCTL is the modulation control register of UCA1

  5. Generation of baud rate

    The USCI baud rate generator can generate standard baud rates from non-standard source frequencies. Two operating modes are provided by the system through the UCOS16-bit selection. The baud rate can be generated by using BRCLK. According to the UCSSELx setting, BRCLK can be used as the clock source of the external clock UCAxCLK or the internal clock ACLK or SMCLK. 

  5.1 Low frequency baud rate

     When UCOS16=0, low frequency mode is selected. This mode allows the baud rate to be generated from a low frequency clock source (for example, 9600 baud from a 32768Hz crystal). By using a lower input frequency, the power consumption of the module can be reduced. Using this mode at high frequency and high division settings will cause the majority voting to be performed in a gradually shrinking window, thus reducing the advantage of majority voting (the examples below are all in this mode).

    In low frequency mode, the baud rate generator uses a prescaler and a modulator to generate the bit clock timing. In this combination, fractional division is supported when generating the baud rate; in this mode, the maximum USCI baud rate is 1/3 of the UART source clock frequency BRCLK.

    The timing of each bit is shown in the figure. For each bit received, a majority vote is used to determine the value of the bit. These sampling points occur at N/2-1/2, N/2 and N/2 + 1/2 BRCLK cycles, where N is the number of BRCLKs in each BITCLK clock. 

    The modulation is based on the UCBRSx settings as shown in Table 15-2. A 1 in the table indicates that m = 1, and the corresponding BITCLK period is one BRCLK period, which is longer than the BITCLK period when m = 0. The modulation is performed after 8 bits, but restarted with a new start bit.

  5.2 Generation of Oversampling Baud Rate

    When UCOS16=1, the oversampling mode is selected. This mode supports sampling of the UART bit stream at a higher input clock frequency. The result of the majority voting method is always at the 1/16 position of a bit clock period. When the IrDA encoder and decoder are enabled, this mode also supports IrDA pulses with 3/16 bit time. 

    This mode uses a prescaler and modulator to generate a BITCLK16 clock that is 16 times faster than BITCLK. This combination allows for fractional divisions of BITCLK16 and BITCLK for baud rate generation. In this case, the maximum USCI baud rate is 1/16 of the UART source clock frequency, BRCLK. When UCBRx is set to 0 or 1, the first stage divider and modulator are ignored and BRCLK equals BITCLK16—in this case BITCLK16 is not modulated, so the UCBRFx bit is ignored. 

    BITCLK16 modulation is based on the UCBRFx settings as shown in Table 15-3. A 1 in the table means that the corresponding BITCLK16 period is one BRCLK period, which is longer than the BITCLK16 period when m=0. Modulation starts with each new bit timing; BITCLK modulation is based on the UCBRSx settings as described above (see Table 15-2).

  5.3 Setting the baud rate

    The baud rate setting of 430 is implemented with three registers: 
    UxBR0: the lower 8 bits of the baud rate generator frequency division coefficient;
    UxBR1: the upper 8 bits of the baud rate generator frequency division coefficient;
    UxMCTL: the fractional part of the baud rate generator frequency division coefficient; 
    for a given BRCLK clock source, the baud rate used will determine the frequency division factor N: N = fBRCLK/baud rate. The frequency division factor N is usually not an integer value, so at least one divider and one modulator are required to get as close to the frequency division factor as possible. If the N value is equal to or greater than 16, the oversampling baud rate generation mode can be selected by setting UCOS16. 

    In low-frequency mode, the integer part of the division factor is implemented by the prescaler UCBRx = INT(N);
    the fractional part is implemented by the modulator with the following nominal formula: UCBRSx = round((N–INT(N))× 8), (round means rounding)
The UCBRSx count value is increased or decreased by 1, giving a smaller maximum bit error for any given bit. In order to detect whether this is the case, detailed error calculations must be performed for each bit of the UCBRSx setting;

   In oversampling mode, the prescaler setting is: UCBRx = INT(N/16), the first order modulator setting is: UCBRFx = round(((N/16)– INT(N/16) ) × 16 ), and the UCBRSx modulator can achieve values ​​from 0 to 7 when higher accuracy is required. To find the lowest maximum bit error rate setting for a given bit, detailed error calculations must be performed for all settings of UCBRSx from 0 to 7 with the initial UCBRFx setting and the UCBRFx settings that increase or decrease by 1. 

The following is a detailed explanation of the four statements in the above example:

  UCA1CTL1 |= UCSSEL_2;                     // SMCLK
  UCA1BR0 = 216;                            // 24MHz 115200
  UCA1BR1 = 0;                              // 24MHz 115200
  UCA1MCTL = UCBRS_2 + UCBRF_0;             // 0x04+0x00

    Here SMCLK has been initialized in the clock part, and its clock source is: Fdcoclkdiv = (760+1)*32768 = 24.936448 MHZ;
the division coefficient N = 24936448/115200 = 216.462222, UCA1BR0 is the lower 8 bits of the integer part of the division system, and UCA1BR1 is the upper 8 bits, so...
UCA1MCTL is the decimal part of the baud rate generator division coefficient. Since it is in low-frequency mode (UCOS16=0), the UCBRFx bit in the UCA1MCTL register is ignored, and UCBRSx = round((N–INT(N))× 8), that is, UCBRSx = 0.46×8, rounded to 4.
   The value of UCBRSx can also be explained as follows: 0.46*8=3.68 is rounded to 4 1s, and these 4 1s are divided into 8 bits and evenly arranged as 01010101 (LSB first). By comparing Table 15-2, we can find that UCBRSx=0x04.