Exynos4412 clock system analysis

In the chip manual, "Clock Management Unit" is abbreviated as CMU. CMU_XXX means "CMU in XXX module", such as CMU_CPU.

For PC, CPU, memory, motherboard, sound card, graphics card, etc., these functional components are composed of different chips and are physically independent of each other. In embedded systems, a chip often integrates multiple functions. For example, Exynos 4412 has both CPU, audio/video interface, LCD interface, GPS and other modules. This type of chip is called SoC, which means System on Chip.

1. Exynos4412 clock system

Different modules often work at different frequencies. It is basically impossible to use a single clock design on a chip. In SoC design, a multi-clock domain design is adopted. The 4412 has 5 clock domains, as shown in the following figure:

The five clock domain names are as follows (BLK in the following text represents block, module):

①CPU_BLK:

It contains Cortex-A9 MPCore processor, L2 cache controller, CoreSight (for debugging). CMU_CPU is used to generate clocks for these components.

② DMC_BLK:

It contains DRAM memory controller (DMC), security sub system, and Generic Interrupt Controller (GIC). CMU_DMC is used to generate clocks for these components.

③LEFTBUS_BLK and RIGHTBUS_BLK:

They are global data buses used to transfer data between DRAM and other submodules.

④ Other BLK: In the above picture, the module circled with a brush.

CMU_TOP is used to generate clocks for these modules.

Exynos4412 has 3 initial clock sources:

① XRTCXTI pin: connected to a 32KHz crystal oscillator, used for real-time clock (RTC).

② XXTI pin: connected to a 12M ~ 50 MHz crystal oscillator, used to provide clock to the system, and can also be left unconnected.

③ XUSBXTI pin: connected to a 24MHz crystal oscillator to provide clock to the system.

In the development board of Friendly Arm, there is no external crystal oscillator on XRTCXTI. The system clock source is the 24MH crystal oscillator connected to the XUSBXTI pin, as shown in the following figure:

From the schematic diagram, we can see that the 4412 development board is connected to a 24MHz crystal oscillator; but the CPU frequency of the 4412 can reach 1.4GHz. It can be imagined that there must be a hardware component to increase the frequency of 24MHZ to 1.4GHZ. This component is called PLL (phase-locked loop). Other components inside the 4412 also need to work at a certain frequency, such as UART, DDR, etc., and there should also be a PLL to increase the frequency of 24MHZ and supply them.

4412 has 4 PLLs: APLL, MPLL, EPLL and VPLL; 2 PHYs: USB PHY and HDMI PHY (PHY: physical layer, generally refers to the chip that interfaces with external signals):

① APLL: used for CPU_BLK; as a supplement to MPLL, it can also provide clocks for DMC_BLK, LEFTBUS_BLK, RIGHTBUS_BLK and CMU_TOP.

② MPLL: for DMC_BLK, LEFTBUS_BLK, RIGHTBUS_BLK and CMU_TOP

③ EPLL: Mainly provides clock for audio module

④ VPLL: Mainly provides 54MHz clock to the video system and clock to G3D (3D graphics accelerator).

⑤ USB PHY: Provides 30MHz and 48MHz clocks to the USB subsystem.

⑥ HDMI PHY: Generates 54MHz clock.

2. How to set PLL in Exynos4412 (taking APLL as an example)

APLL clock flow chart

Taking the above picture as an example, there are three concepts involved:

① MUX: multiplexing, that is, selecting one from multiple input sources

② PLL: boosts the low-frequency input clock and outputs it

③ DIV: Divider, which reduces the frequency of the high-frequency input clock and outputs it

From the clock flow chart of APLL, we can know that its clock source can be the crystal oscillator connected to the XXTI pin or the crystal oscillator connected to the XUSBXTI pin, which is selected by the MUX on the left side of the above figure. The output of this MUX is called FINPLL.

By setting the register of APLL (selecting the parameter value according to the formula), FINPLL can be increased to a certain frequency output, assuming it is 1.4GHz. It is named FOUTAPLL in the figure.

Continue to look at the picture to the right, there are multiple DIVs, you can set the corresponding registers to lower the frequency. The CPU can work at 1.4GHz, but other modules cannot work at such a high frequency, so the frequency must be lowered.

The process of setting up PLL is as follows:

① Set the P, M, and S values ​​of the PLL, which are calculated using the formula based on the expected frequency.

② Set other control parameters of PLL

③ Enable PLL

④ PLL will wait for a while for the clock to stabilize

⑤ Set MUX and select the clock output by PL

Simply put: setup first, start second, and use third.

Point 5 means: if the PLL is currently being used, first set the MUX to use another clock source or disable the use of the PLL. After setting the PLL, set the MUX again to change back to the original PLL clock.

3. PLL Register

The register functions of the four PLLs are similar. These registers can be divided into six categories, as shown in the following figure:

PLL register classification

Take APLL as an example:

(1) APLL_LOCK (address: 0x10044000 )

APLL_LOCK

Note: After setting the parameters of APLL and enabling it, APLL cannot output a stable clock immediately. It needs to go through a lock time. The maximum lock time of APLL is: (270 x PDIV) cycles. So setting APLL_LOCK to (270 x PDIV) is sufficient.

PDIV is introduced in the APLL_CON1 register below

(2) APLL_CON0 (address: 0x10044100 ) (only the useful bits are listed here)

APLL_CON0

Based on the values ​​of M, P, and S, the output clock of APLL can be calculated:

FOUT = MDIV x FIN / (PDIV x 2^SDIV)

The values ​​of M, P, and S cannot be taken randomly and need to meet certain restrictions (please refer to the chip manual). The chip manual gives recommended values.

(3) APLL_CON1 (address: 0x10044104) (only useful bits are listed here)

APLL_CON1

This register is used to set the BYPASS mode, that is, whether the APLL directly outputs the FIN clock or outputs the clock after increasing the frequency; it is also used to set the AFC (automatic frequency control) function, which is temporarily ignored. The default value of this register can be used.

(4) CLK_SRC_CPU (address: 0x10044200)

CLK_SRC_CPU

Refer to the APLL clock flow chart above:

① BIT[0] controls the first MUX (i.e. MUXAPLL) and is used to select whether to use the output clock of FIN or APLL. This output is called MOUTAPLL.

② BIT[16] controls the second MUX (i.e. MUXCORE) to select MOUTAPLL or SCLKMPLL. SCLKMPLL is controlled by the following MUXMPLL.

③ BIT[24] controls the third MUX (i.e., MUXMPLL) to select FINPLL or FOUTMPLL, and this output is called SCLKMPLL. Among them, FOUTMPLL comes from the output of MPLL.

④ BIT[20] controls the fourth MUX (i.e., MUXHPM) and is used to select MOUTAPLL or SCLKMPLL.

(5) CLK_MUX_STAT_CPU (address: 0x10044400):

CLK_MUX_STAT_CPU

Used to read the MUX status set in the CLK_SRC_CPU register.

(6) CLK_DIV_CPU0 (address: 0x10044500), CLK_DIV_CPU1 (address: 0x10044504)

CLK_DIV_CPU

Refer to the APLL clock flow chart above, take the CPU operating frequency ARMCLK as an example, and calculate the frequency of ARMCLK according to the above figure:

ARMCLK = output of MUXCORE / DIVCORE / DIVCORE2

= MOUTCORE / (CORE_RATIO + 1) / DIVCORE2

= MOUTCORE / (CORE_RATIO + 1) / (CORE2_RATIO + 1)

MOUTCORE represents the output of MUXCORE. When MUXAPLL is 1 and MUXCORE is 0, it is equal to "MDIV x FIN / (PDIV x 2 ^ SDIV), that is, APLL output FOUT"

(7) CLK_DIV_STAT_CPU0 (address: 0x10044600), CLK_DIV_STAT_CPU1 (address: 0x1004 604)

Used to determine whether the divider output has stabilized after setting the divider parameters.

(8) CLK_GATE_IP_CPU (address: 0x10044900)

CLK_GATE_IP_CPU

It is used to control whether to provide clock to a certain module. Ignore it for now.

Well, this is the end of the introduction to the Exynos clock system. In the next section, we will start doing clock-related experiments.