1. Overview

S5M8767A has 9 BUCKs and 28 LDOs, which can be considered as a total of 37 power supply circuits. These 37 power supply circuits can use a minimum step voltage of 6.25mV, and up to 60 voltage levels can achieve precise control of the output voltage. In addition, S5M8767A also has a hardware RTC that can save clock information when powered by an external battery.

2. The relationship between PMIC and uboot

Uboot initializes hardware by module and has its own code sequence, which requires PMIC to provide power to specific hardware in advance at a specific time point for uboot to initialize and configure. Otherwise, the execution of uboot will inevitably fail. For example, PMIC needs to supply power to its two power supplies before eMMC is initialized.

In addition, the initialization time of PMIC has a default time point in uboot, but this time point is still closely related to the actual circuits of the core board and the baseboard, and needs to be advanced or delayed according to actual needs.

2.0 Classification of Buck and LDO in PMIC

The BUCK and LDO in PMIC can be roughly divided into two types:

One is the BUCK and LDO that can directly output voltage when the PMIC is powered on.

The other is that the PMIC does not output voltage when powered on, and the BUCK and LDO can only output voltage after the PMIC is configured using i2c.

2.1 Relationship between PMIC and DDR

For 4412, DDR initialization is performed in BL2. At this time, I feel that it is meaningless to use the assembly initialization hardware i2c to configure the PMIC. Therefore, the DDR power supply needs to be connected to the default ON BUCK of the PMIC, that is, the BUCK that can directly output voltage when the PMIC is powered on, without code configuration.

S5M8767A recommends using BUCK5 as the power supply for DDR.

BUCK5

However, the default output of BUCK5 is 1.2V, and DDR requires the standard 1.5V. What's the problem?

Samsung has already considered this issue for us. In order to adapt to different types of DDR, BUCK5 can output four default voltages by matching the levels of the two pins K9 and K10:

V select

V SET

Here, the board is set up like this:

board set

In this way, B5S1:B5S2 = 1:0, that is, BUCK5 outputs a 1.5V voltage, which just meets the requirements of DDR.

2.2 Relationship between PMIC and 4412 main chip

The ARM core is supplied with voltage by the PMIC's BUCK2, which is also turned on by default and outputs 1.1 V by default. After consulting the 4412 spec, it should be noted that at 1.1 V, the APLL that provides the clock to the ARM core can only output a maximum of 1000 MHz, that is, if the PMIC is not set when the power is just turned on, the ARM core can only operate at 1000 MHz and cannot use the highest frequency of 1.4 GHz.

3. PMIC Setting Method

3.1 Communication Protocol

        S5M8767A uses I2C protocol to communicate with 4412. The slave address is divided into two parts, PM (Power Manager) and RTC. That is to say, the register addresses of PM and RTC are separate and can be regarded as two separate chips.

PM

3.2 Examples

The following uses BUCK1 as an example to explain the register setting method. Other BUCKs and LDOs are basically similar. Just read the manual carefully when necessary:

BUCK1 has two 8-bit control registers.

CTRL1

The lower 6 bits of CTRL1 can be set according to the default value, and the upper two bits need to be explained. The meaning of 00 and 1x is self-explanatory. 01 means that the switch of BUCK1 is controlled by the PWREN external pin, and this PWREN pin is generally connected to the XPWRRGTON pin of 4412. This XPWRRGTON is automatically controlled by the CPU. When the CPU is in sleep mode, this pin is low, and when it is in working mode, this pin is high. That is to say, once the CPU exits sleep mode, the PMIC will power on all BUCK & LDO controlled by PWREN.

CTRL2

CTRL2 is used to control the output voltage of BUCK2, with a step value of 6.25mV. You can calculate the required voltage and then write it in.

Literacy

What is PMU (PMIC)

PMU (power management unit) is a highly integrated power management solution for portable applications. It combines several traditional discrete power management chips, such as low-dropout linear regulators (LDO) and DC/DC converters, into a mobile phone's power management unit (PMU). This can achieve higher power conversion efficiency and lower power consumption, as well as fewer components to fit into smaller board space and lower costs.

As a power management integrated unit for specific main chips of consumer electronics (mobile phones, MP4, GPS, PDA, etc.), PMU can provide all the power supplies with different voltages required by the main chip, and supply the same voltage energy to different mobile phone working units, such as processors, RF devices, camera modules, etc., so that these units can work normally. According to the needs of the main chip, it integrates power management, charging control, and power on/off control circuits. It includes adaptive USB-Compatible PWM charger, multi-channel DC-DC converter (BuckDC-DCconverter), multi-channel linear regulator (LDO), Charge Pump, RTC circuit, motor drive circuit, LCD backlight drive circuit, keyboard backlight drive circuit, keyboard controller, voltage/current/temperature multi-channel 12-BitADC, and multi-channel configurable GPIO. In addition, it also integrates over/under voltage (OVP/UVP), over temperature (OTP), over current (OCP) and other protection circuits. Advanced PMU can safely and transparently distribute power between USB and external AC adapter, lithium battery and application system load. Dynamic Power Path Management (DPPM) shares the AC adapter current between the system and battery charging, and automatically reduces the charging current when the system load increases. Adjust the charging current and system current distribution relationship to maximize the normal operation of the system. When charging through the USB port, if the input voltage drops below the threshold to prevent the USB port from crashing, the input voltage-based dynamic power management (IDPM) reduces the input current. When the adapter cannot provide peak system current, the power path architecture also allows the battery to compensate for such system current requirements.
LDO is a voltage regulator that uses a lower operating voltage difference to adjust the output voltage through negative feedback to keep it constant. If the voltage difference is small, use LDO, which is convenient for power management with a shutdown function. If the voltage difference is large, it is more efficient to use DC-DC.

Power supplies that can provide multiple voltages as needed by the system are required for voltage regulation. In addition, these power supplies can also turn on and off these supply voltages in sync with the functions to support voltage domain switching.

PMU is usually customized and bound to the main chip. Because it has to cooperate with the power-on timing of the CPU. The power-on sequence of certain voltages and the time intervals between them have a sequence relationship and time requirements. This is masked. PMU is actually a dedicated power controller with a mask program. It requires a 32.768KHZ crystal and a 19.2M crystal. The 32.768KHZ crystal works in standby mode, and the 19.2M main crystal works in normal operation.

After the battery is connected, the PMIC enters the standby state. The PMU is clocked by a 32.768KHZ crystal. After the POWER button is pressed to trigger the startup, the corresponding LDO and DC-DC are turned on according to the customized startup sequence. The 19.2M main clock works. After the CPU power is normal, the output is set to the CPU, the reset signal is output to the CPU, the reset signal is released, and the CPU starts to start. The CPU outputs the PS_HOLD signal to put the PMIC in the working state. (When shutting down, the CPU pulls down the PS_HOLD power, and the PMIC is turned off and enters the shutdown state)

After the CPU works normally, the various modules of PMIC can be controlled through the I2C interface. For example, when the system frequency is changed, the core voltage needs to be adjusted to the corresponding voltage for different operating frequencies. RTC time setting and ALARM clock. At the same time, PMIC can generate interrupt signals for abnormal events to the CPU, and the CPU will then handle the interrupt.

The more power supplies the PMIC has, the finer the power supply to the system modules is, and the less affected the power supply of each module is, so more power is saved.