STM32F103ZET6 — IWDG

Introduction

First, let me briefly introduce the role of the watchdog.

The watchdog is used to prevent the system from encountering various abnormal situations during operation, which may cause the program to stop running. It can be understood that the watchdog is a guarantee that can save the system from entering an abnormal situation and the system cannot continue to work. When the system starts the watchdog function, the counter starts counting. Before the counter finishes counting, the system program must "feed the dog" to let the watchdog know that the system is still "alive". If the system does not "feed the dog" at the specified time, the watchdog generates a reset signal and the system restarts from Reset.

From the perspective of system implementation, the watchdog is actually just a counter. When the count reaches the end point, a reset signal is generated. If the count does not reach the end point, the software intervenes and feeds the watchdog, the counter will count again and no reset will be generated.

STM32 has two types of watchdogs: independent watchdog (IWDG) and window watchdog (WWDG).

This article mainly introduces the usage of independent watchdog IWDG.

clock

The STM32 independent watchdog clock is provided by the LSI low-frequency RC oscillator. The LSI clock frequency is about 40kHz (between 30kHz and 60kHz). So, if you want to use this thing, should you manually turn on the LSI clock like other peripherals?

The answer is, you can do it, and you can’t!

because:

It can be seen that the LSI will be forced to turn on. Therefore, as long as the gatekeeper is started, the LSI will be forced to turn on. This means that we do not need to manually turn on the LSI clock.

working principle

IWDG is most suitable for applications where the watchdog needs to work completely independently outside the main program and has low requirements on time accuracy.

• IWDG with free-running down counter

• Clock provided by independent RC oscillator (operable in stop and standby modes)

• When the watchdog is activated, a reset occurs when the counter counts to 0x000.

The structural block diagram is shown in the figure:

The main ones include:

The pre-divider of IWDG_PR divides the 40kHZ clock from LSI.

IWDG_RLR reload register, which is the starting value of the counter decrement

The IWDG_KR key register is responsible for executing the command:

    1. Write 0xAAAA to feed the dog

    2. Write 0x5555 to allow access to the IWDG_PR and IWDG_RLR registers

    3. Write 0xCCCC to start the watchdog

Configuration Process

So the usage and configuration process of IWDG is as follows:

1. Turn on the LSI clock and wait for it to become valid

2. Write 0x5555 to IWDG_KR to allow access to other registers.

3. Write the prescaler value to 4 (i.e. 64 division)

4. Set the timer value to 625 (resulting in a 1s timeout)

5. Write 0xAAAA to IWDG_KR to avoid reset

6. Write 0xCCCC to IWDG_KR to enable the watchdog function.

Note: Use 0xAAAA to write to IWDG_KR to implement the dog feeding function. If the dog is not fed regularly, a reset interrupt will be generated.

Code

/*

 ***************************************************************

 ******************* IWDG Function Defination *******************

 ***************************************************************

*/

#define SK_IWDG_PER             4   // 64 Prescaler divider to 625

#define SK_IWDG_CNT             625 // 1s timeout

void SK_IWDGInit(uint16_t prer, uint16_t wdg_value)

{

    // First Open LSI Clock for IWDG

    RCC_LSICmd(ENABLE);

    while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET);

    // If use IWDG, LSI will be opened force

    IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

    // Set Prescaler

    IWDG_SetPrescaler(prer);

    // Set reload value

    IWDG_SetReload(wdg_value);

    // Set 0xAAAA To make sure not go into reset

    IWDG_ReloadCounter();

    // Enable WDG

    IWDG_Enable();

}

void SK_IWDGFeed(void)

{

    IWDG_ReloadCounter();

}