STM32 system clock configuration

1. Clock drive 
There are three different clock sources that can be used to drive the system clock: 
● Internal high-speed (HSI) 8MHz RC oscillator clock 
● External high-speed (HSE) oscillator clock 
● PLL clock

2. Introduction to system clock 
In STM32, when we say we want to configure the system clock, we mean to configure the red part "SYSCLK (system clock)" in the figure below. The system clock SYSCLK is the clock source for most of the working periods in STM32. As shown in the figure below, the system clock can be configured for IIC, AHB, APB, DMA and other clocks. 

3. Example of system clock configuration 
: If an 8MHZ crystal oscillator is connected externally, it needs to be configured as a 48MHZ system clock. 
Analysis: Because we need to use an 8MHZ external clock to get a 48MHZ system clock, we need to multiply it by 6 times without frequency division to get the system clock. Therefore, the route I plan to configure is shown in the figure below. 
 
3.1 Because we need to get a 48MHZ system clock, we use the HSE external oscillator clock to drive it. In the RCC->CR register, the HSEON bit is set to 1, which means that the HSE oscillator is turned on; 
3.2 It is set by hardware to indicate whether the HSE oscillator is stable. Still in the RCC-CR register, when the HSE oscillator is ready, the hardware will set the HSERDY bit to 1. 
3.3 It should be clear from the figure that the next step is to perform the RCC->CFGR2 register example PREDIV frequency division operation, but please note that PREDIV[3:0] PREDIV frequency division factor 
These bits are used to set or clear the PREDIV frequency division factor. These bits can only be rewritten when the PLL is turned off. So the PLL should be turned off before this. So turn off PLLON in the RCC->CR register. Wait for the PLLRDY bit to lock. 
3.4 Start the PREDIV division operation of the RCC->CFGR2 register, but because we do not divide but multiply, the PREDIV[3:0] PREDIV division factor is 0000 (no division). 
3.5 Start by setting the PLLSRC (input clock source) switch in RCC->CFGR to 1 to select HSE/PREDIB as the PLL input clock. And enter the PLLMUL in RCC->CFGR to select the multiplication. We want 6 times the frequency, so select the multiplication factor of 6 (0100) 
3.6 After the multiplication is completed, enable the PLLON bit of the RCC->CR register, and wait for the hardware to set the PLLRDY in the RC->CR register. 
3.7 Select the PLLCLK output as the system clock when passing the SW switch 
3.8 Enable the GPIO clock

void SystemClock(void) 
{ 
RCC->CR|=RCC_CR_HSEON; 
while(!(RCC->CR&RCC_CR_HSERDY)); 
RCC->CR&=~RCC_CR_PLLON; 
while(RCC->CR&RCC_CR_PLLRDY); 
RCC->CFGR2=RCC_CFGR2_PREDIV_DIV1; 
RCC->CFGR=RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL6; 
RCC->CR|=RCC_CR_PLLON; 
while(!RCC->CR&RCC_CR_PLLRDY); 
RCC->CFGR=(RCC->CFGR&~RCC_CFGR_SW)|RCC_CFGR_SW_PLL; 
while((RCC->CFGR&RCC_CFGR_SWS)!=RCC_CFGR_SWS_1); 
RCC->AHBENR|=RCC_AHBENR_GPIOAEN; 
return; 
}