STM32 TIM1 PWM has no output

The CHN1 and CHN4 of TIM1 are set to output PWM. The code is as follows, but the simulated waveform is incorrect and the upper device is also incorrect:

RCC->APB2ENR|=1<<11; //TIM1 clock enable       

RCC->APB2ENR|=1<<2; //Enable PORTA clock  

GPIOA->CRH&=0XFFFFFFF0; //PA8 output

GPIOA->CRH|=0X0000000B; //General push-pull output  

GPIOA->ODR|=1<<8; //PA8 pull-up

GPIOA->CRH&=0XFFFF0FFF; //PA11 output

GPIOA->CRH|=0X0000B000; //General push-pull output  

GPIOA->ODR|=1<<11; //PA11 pull-up

TIM1->ARR=arr; //Set the counter to automatically reload value 

TIM1->PSC=psc; //Prescaler does not divide

TIM4->ARR=arr; //Set the counter to automatically reload value 

TIM4->PSC=psc; //Prescaler does not divide

TIM1->CCMR1|=6<<4; //CH1 PWM2 mode  

TIM1->CCMR1|=1<<3; //CH1 preload enable   

TIM1->CCMR2|=7<<12; //CH4 PWM2 mode  

TIM1->CCMR2|=1<<11; //CH4 preload enable   

TIM1->CCER|= pwdState << 0; //OC1 output enable   

TIM1->CCER|= pwdState << 12; //OC1 output enable   

TIM1->CR1=0x8000; //ARPE enable 

TIM1->CR1|=0x01; //Enable timer 1  

Checking the register manual, I found that TIM1 has a MOE bit that controls the output of TIM1: MOE: Main output enable Bit 15 Once the brake input is valid, this bit is cleared to '0' asynchronously by hardware. Depending on the setting value of the AOE bit, this bit can be cleared to '0' by software or automatically set to 1. It is only valid for channels configured as outputs. 0: Disable OC and OCN outputs or force them to idle state; 1: If the corresponding enable bit (CCxE, CCxNE bits of the TIMx_CCER register) is set, OC and OCN outputs are turned on. For details on OC/OCN enable, see 13.4.9 TIM1 and TIM8 capture/compare enable register (TIMx_CCER).

Add the following code and the output will be normal:        

                     TIM1->BDTR |= 1<<15;